mtd: denali.c: fixed all open brace { check-patch errors
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Chuanxiao Dong
David Woodhouse
parent
5bac3acfb8
commit
345b1d3b46
@ -211,9 +211,7 @@ static void reset_bank(struct denali_nand_info *denali)
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status & operation_timeout[denali->flash_bank])
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{
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printk(KERN_ERR "reset bank failed.\n");
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}
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}
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/* Reset the flash controller */
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@ -637,14 +635,12 @@ static void find_valid_banks(struct denali_nand_info *denali)
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}
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}
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if (denali->platform == INTEL_CE4100)
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{
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if (denali->platform == INTEL_CE4100) {
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/* Platform limitations of the CE4100 device limit
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* users to a single chip solution for NAND.
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* Multichip support is not enabled.
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*/
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if (denali->total_used_banks != 1)
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{
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if (denali->total_used_banks != 1) {
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printk(KERN_ERR "Sorry, Intel CE4100 only supports "
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"a single NAND device.\n");
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BUG();
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@ -888,9 +884,7 @@ static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali)
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* with a specific ONFI mode, we apply those changes here.
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*/
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if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
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{
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NAND_ONFi_Timing_Mode(denali, onfi_timing_mode);
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}
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return status;
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}
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@ -997,9 +991,7 @@ static void print_irq_log(struct denali_nand_info *denali)
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printk("ISR debug log index = %X\n", denali->idx);
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for (i = 0; i < 32; i++)
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{
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printk("%08X: %08X\n", i, denali->irq_debug_array[i]);
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}
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}
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#endif
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@ -1018,12 +1010,10 @@ static irqreturn_t denali_isr(int irq, void *dev_id)
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/* check to see if a valid NAND chip has
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* been selected.
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*/
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if (is_flash_bank_valid(denali->flash_bank))
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{
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if (is_flash_bank_valid(denali->flash_bank)) {
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/* check to see if controller generated
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* the interrupt, since this is a shared interrupt */
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if ((irq_status = denali_irq_detected(denali)) != 0)
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{
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if ((irq_status = denali_irq_detected(denali)) != 0) {
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#if DEBUG_DENALI
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denali->irq_debug_array[denali->idx++] = 0x10000000 | irq_status;
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denali->idx %= 32;
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@ -1054,8 +1044,7 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
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bool retry = false;
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unsigned long timeout = msecs_to_jiffies(1000);
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do
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{
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do {
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#if DEBUG_DENALI
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printk("waiting for 0x%x\n", irq_mask);
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#endif
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@ -1068,8 +1057,7 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
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denali->idx %= 32;
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#endif
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if (intr_status & irq_mask)
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{
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if (intr_status & irq_mask) {
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denali->irq_status &= ~irq_mask;
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spin_unlock_irq(&denali->irq_lock);
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#if DEBUG_DENALI
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@ -1077,9 +1065,7 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
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#endif
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/* our interrupt was detected */
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break;
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}
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else
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{
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} else {
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/* these are not the interrupts you are looking for -
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* need to wait again */
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spin_unlock_irq(&denali->irq_lock);
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@ -1092,8 +1078,7 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
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}
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} while (comp_res != 0);
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if (comp_res == 0)
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{
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if (comp_res == 0) {
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/* timeout */
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printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
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intr_status, irq_mask);
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@ -1149,22 +1134,17 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
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addr = BANK(denali->flash_bank) | denali->page;
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if (op == DENALI_WRITE && access_type != SPARE_ACCESS)
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{
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if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
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cmd = MODE_01 | addr;
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denali_write32(cmd, denali->flash_mem);
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}
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else if (op == DENALI_WRITE && access_type == SPARE_ACCESS)
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{
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} else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
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/* read spare area */
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cmd = MODE_10 | addr;
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index_addr(denali, (uint32_t)cmd, access_type);
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cmd = MODE_01 | addr;
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denali_write32(cmd, denali->flash_mem);
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}
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else if (op == DENALI_READ)
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{
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} else if (op == DENALI_READ) {
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/* setup page read request for access type */
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cmd = MODE_10 | addr;
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index_addr(denali, (uint32_t)cmd, access_type);
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@ -1173,13 +1153,10 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
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use the pipeline commands in Spare area only mode. So we
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don't.
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*/
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if (access_type == SPARE_ACCESS)
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{
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if (access_type == SPARE_ACCESS) {
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cmd = MODE_01 | addr;
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denali_write32(cmd, denali->flash_mem);
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}
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else
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{
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} else {
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index_addr(denali, (uint32_t)cmd, 0x2000 | op | page_count);
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/* wait for command to be accepted
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@ -1187,14 +1164,11 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
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* bank. */
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0)
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{
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if (irq_status == 0) {
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printk(KERN_ERR "cmd, page, addr on timeout "
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"(0x%x, 0x%x, 0x%x)\n", cmd, denali->page, addr);
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status = FAIL;
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}
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else
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{
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} else {
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cmd = MODE_01 | addr;
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denali_write32(cmd, denali->flash_mem);
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}
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@ -1216,9 +1190,7 @@ static int write_data_to_flash_mem(struct denali_nand_info *denali, const uint8_
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/* write the data to the flash memory */
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buf32 = (uint32_t *)buf;
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for (i = 0; i < len / 4; i++)
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{
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denali_write32(*buf32++, denali->flash_mem + 0x10);
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}
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return i*4; /* intent is to return the number of bytes read */
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}
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@ -1241,9 +1213,7 @@ static int read_data_from_flash_mem(struct denali_nand_info *denali, uint8_t *bu
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/* transfer the data from the flash */
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buf32 = (uint32_t *)buf;
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for (i = 0; i < len / 4; i++)
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{
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*buf32++ = ioread32(denali->flash_mem + 0x10);
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}
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return i*4; /* intent is to return the number of bytes read */
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}
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@ -1259,8 +1229,7 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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denali->page = page;
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if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
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DENALI_WRITE) == PASS)
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{
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DENALI_WRITE) == PASS) {
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write_data_to_flash_mem(denali, buf, mtd->oobsize);
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#if DEBUG_DENALI
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@ -1274,14 +1243,11 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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/* wait for operation to complete */
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0)
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{
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if (irq_status == 0) {
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printk(KERN_ERR "OOB write failed\n");
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status = -EIO;
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}
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}
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else
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{
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} else {
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printk(KERN_ERR "unable to send pipeline command\n");
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status = -EIO;
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}
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@ -1300,8 +1266,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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printk("read_oob %d\n", page);
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#endif
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if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
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DENALI_READ) == PASS)
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{
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DENALI_READ) == PASS) {
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read_data_from_flash_mem(denali, buf, mtd->oobsize);
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/* wait for command to be accepted
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@ -1310,9 +1275,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0)
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{
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printk(KERN_ERR "page on OOB timeout %d\n", denali->page);
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}
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/* We set the device back to MAIN_ACCESS here as I observed
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* instability with the controller if you do a block erase
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@ -1340,12 +1303,8 @@ bool is_erased(uint8_t *buf, int len)
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{
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int i = 0;
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for (i = 0; i < len; i++)
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{
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if (buf[i] != 0xFF)
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{
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return false;
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}
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}
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return true;
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}
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#define ECC_SECTOR_SIZE 512
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@ -1362,15 +1321,13 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
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{
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bool check_erased_page = false;
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if (irq_status & INTR_STATUS0__ECC_ERR)
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{
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if (irq_status & INTR_STATUS0__ECC_ERR) {
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/* read the ECC errors. we'll ignore them for now */
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uint32_t err_address = 0, err_correction_info = 0;
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uint32_t err_byte = 0, err_sector = 0, err_device = 0;
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uint32_t err_correction_value = 0;
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do
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{
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do {
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err_address = ioread32(denali->flash_reg +
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ECC_ERROR_ADDRESS);
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err_sector = ECC_SECTOR(err_address);
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@ -1383,29 +1340,23 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
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ECC_CORRECTION_VALUE(err_correction_info);
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err_device = ECC_ERR_DEVICE(err_correction_info);
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if (ECC_ERROR_CORRECTABLE(err_correction_info))
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{
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if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
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/* offset in our buffer is computed as:
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sector number * sector size + offset in
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sector
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*/
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int offset = err_sector * ECC_SECTOR_SIZE +
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err_byte;
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if (offset < denali->mtd.writesize)
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{
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if (offset < denali->mtd.writesize) {
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/* correct the ECC error */
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buf[offset] ^= err_correction_value;
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denali->mtd.ecc_stats.corrected++;
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}
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else
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{
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} else {
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/* bummer, couldn't correct the error */
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printk(KERN_ERR "ECC offset invalid\n");
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denali->mtd.ecc_stats.failed++;
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}
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}
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else
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{
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} else {
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/* if the error is not correctable, need to
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* look at the page to see if it is an erased page.
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* if so, then it's not a real ECC error */
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@ -1482,8 +1433,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
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/* copy buffer into DMA buffer */
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memcpy(denali->buf.buf, buf, mtd->writesize);
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if (raw_xfer)
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{
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if (raw_xfer) {
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/* transfer the data to the spare area */
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memcpy(denali->buf.buf + mtd->writesize,
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chip->oob_poi,
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@ -1500,8 +1450,7 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
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/* wait for operation to complete */
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0)
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{
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if (irq_status == 0) {
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printk(KERN_ERR "timeout on write_page (type = %d)\n", raw_xfer);
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denali->status =
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(irq_status & INTR_STATUS0__PROGRAM_FAIL) ? NAND_STATUS_FAIL :
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@ -1584,21 +1533,15 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
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check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status);
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denali_enable_dma(denali, false);
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if (check_erased_page)
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{
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if (check_erased_page) {
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read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
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/* check ECC failures that may have occurred on erased pages */
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if (check_erased_page)
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{
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if (check_erased_page) {
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if (!is_erased(buf, denali->mtd.writesize))
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{
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denali->mtd.ecc_stats.failed++;
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}
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if (!is_erased(buf, denali->mtd.oobsize))
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{
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denali->mtd.ecc_stats.failed++;
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}
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}
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}
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return 0;
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@ -1643,9 +1586,7 @@ static uint8_t denali_read_byte(struct mtd_info *mtd)
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uint8_t result = 0xff;
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if (denali->buf.head < denali->buf.tail)
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{
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result = denali->buf.buf[denali->buf.head++];
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}
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#if DEBUG_DENALI
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printk("read byte -> 0x%02x\n", result);
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@ -1708,8 +1649,7 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
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#if DEBUG_DENALI
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printk("cmdfunc: 0x%x %d %d\n", cmd, col, page);
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#endif
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switch (cmd)
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{
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switch (cmd) {
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case NAND_CMD_PAGEPROG:
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break;
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case NAND_CMD_STATUS:
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@ -1717,8 +1657,7 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
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break;
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case NAND_CMD_READID:
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reset_buf(denali);
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if (denali->flash_bank < denali->total_used_banks)
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{
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if (denali->flash_bank < denali->total_used_banks) {
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/* write manufacturer information into nand
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buffer for NAND subsystem to fetch.
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*/
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@ -1727,9 +1666,7 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
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write_byte_to_buf(denali, denali->dev_info.bDeviceParam0);
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write_byte_to_buf(denali, denali->dev_info.bDeviceParam1);
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write_byte_to_buf(denali, denali->dev_info.bDeviceParam2);
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}
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else
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{
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} else {
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int i;
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for (i = 0; i < 5; i++)
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write_byte_to_buf(denali, 0xff);
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@ -1796,20 +1733,24 @@ static void denali_hw_init(struct denali_nand_info *denali)
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static struct nand_ecclayout nand_oob_slc = {
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.eccbytes = 4,
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.eccpos = { 0, 1, 2, 3 }, /* not used */
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.oobfree = {{
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.oobfree = {
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{
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.offset = ECC_BYTES_SLC,
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.length = 64 - ECC_BYTES_SLC
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}}
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}
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}
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};
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#define ECC_BYTES_MLC 14 * (2048 / ECC_SECTOR_SIZE)
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static struct nand_ecclayout nand_oob_mlc_14bit = {
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.eccbytes = 14,
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.eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */
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.oobfree = {{
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.oobfree = {
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{
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.offset = ECC_BYTES_MLC,
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.length = 64 - ECC_BYTES_MLC
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}}
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}
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}
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};
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static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
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@ -1882,8 +1823,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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/* Due to a silicon limitation, we can only support
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* ONFI timing mode 1 and below.
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*/
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if (onfi_timing_mode < -1 || onfi_timing_mode > 1)
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{
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if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
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printk("Intel CE4100 only supports ONFI timing mode 1 "
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"or below\n");
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ret = -EINVAL;
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@ -1912,16 +1852,14 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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/* Is 32-bit DMA supported? */
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ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
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if (ret)
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{
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if (ret) {
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printk(KERN_ERR "Spectra: no usable DMA configuration\n");
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||||
goto failed_enable;
|
||||
}
|
||||
denali->buf.dma_buf = pci_map_single(dev, denali->buf.buf, DENALI_BUF_SIZE,
|
||||
PCI_DMA_BIDIRECTIONAL);
|
||||
|
||||
if (pci_dma_mapping_error(dev, denali->buf.dma_buf))
|
||||
{
|
||||
if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
|
||||
printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
|
||||
goto failed_enable;
|
||||
}
|
||||
@ -1978,8 +1916,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
/* MTD supported page sizes vary by kernel. We validate our
|
||||
* kernel supports the device here.
|
||||
*/
|
||||
if (denali->dev_info.wPageSize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
|
||||
{
|
||||
if (denali->dev_info.wPageSize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
|
||||
ret = -ENODEV;
|
||||
printk(KERN_ERR "Spectra: device size not supported by this "
|
||||
"version of MTD.");
|
||||
@ -2011,8 +1948,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
/* scan for NAND devices attached to the controller
|
||||
* this is the first stage in a two step process to register
|
||||
* with the nand subsystem */
|
||||
if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL))
|
||||
{
|
||||
if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
|
||||
ret = -ENXIO;
|
||||
goto failed_nand;
|
||||
}
|
||||
@ -2029,13 +1965,10 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
|
||||
denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
|
||||
|
||||
if (denali->dev_info.MLCDevice)
|
||||
{
|
||||
if (denali->dev_info.MLCDevice) {
|
||||
denali->nand.ecc.layout = &nand_oob_mlc_14bit;
|
||||
denali->nand.ecc.bytes = ECC_BYTES_MLC;
|
||||
}
|
||||
else /* SLC */
|
||||
{
|
||||
} else {/* SLC */
|
||||
denali->nand.ecc.layout = &nand_oob_slc;
|
||||
denali->nand.ecc.bytes = ECC_BYTES_SLC;
|
||||
}
|
||||
@ -2057,8 +1990,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
denali->nand.ecc.write_oob = denali_write_oob;
|
||||
denali->nand.erase_cmd = denali_erase;
|
||||
|
||||
if (nand_scan_tail(&denali->mtd))
|
||||
{
|
||||
if (nand_scan_tail(&denali->mtd)) {
|
||||
ret = -ENXIO;
|
||||
goto failed_nand;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user