pinctrl: tegra: add support for rcv-sel and drive type
NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e. rcv-sel and drive type. rcv-sel: Select between High and Normal VIL/VIH receivers. RCVR_SEL=1: High VIL/VIH RCVR_SEL=0: Normal VIL/VIH drv_type: Ouptput drive type: 33-50 ohm driver: 0x1 66-100ohm driver: 0x0 Add support of these parameters to be configure from DTS file. Tegra20 and Tegra30 does not support this configuration and hence initialize their pinmux structure with reg = -1. Originally written by Pritesh Raithatha. Changes by ldewangan: - remove drvtype_width as it is always 2. - Better describe the change. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Pritesh Raithatha
Linus Walleij
parent
b2083062a3
commit
348d1bf75c
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@ -201,6 +201,7 @@ static const struct cfg_param {
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{"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
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{"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
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{"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
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{"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
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{"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
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{"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
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{"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
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@ -208,6 +209,7 @@ static const struct cfg_param {
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{"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
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{"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
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{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
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{"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
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};
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static int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
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@ -450,6 +452,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
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*bit = g->ioreset_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_RCV_SEL:
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*bank = g->rcv_sel_bank;
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*reg = g->rcv_sel_reg;
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*bit = g->rcv_sel_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
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*bank = g->drv_bank;
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*reg = g->drv_reg;
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@ -492,6 +500,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
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*bit = g->slwr_bit;
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*width = g->slwr_width;
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break;
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case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
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*bank = g->drvtype_bank;
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*reg = g->drvtype_reg;
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*bit = g->drvtype_bit;
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*width = 2;
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break;
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default:
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dev_err(pmx->dev, "Invalid config param %04x\n", param);
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return -ENOTSUPP;
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@ -30,6 +30,8 @@ enum tegra_pinconf_param {
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_IORESET,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_RCV_SEL,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
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/* argument: Boolean */
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TEGRA_PINCONF_PARAM_SCHMITT,
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@ -43,6 +45,8 @@ enum tegra_pinconf_param {
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TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
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/* argument: Integer, range is HW-dependant */
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TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
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/* argument: Integer, range is HW-dependant */
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TEGRA_PINCONF_PARAM_DRIVE_TYPE,
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};
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enum tegra_pinconf_pull {
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@ -95,6 +99,9 @@ struct tegra_function {
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* @ioreset_reg: IO reset register offset. -1 if unsupported.
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* @ioreset_bank: IO reset register bank. 0 if unsupported.
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* @ioreset_bit: IO reset register bit. 0 if unsupported.
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* @rcv_sel_reg: Receiver select offset. -1 if unsupported.
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* @rcv_sel_bank: Receiver select bank. 0 if unsupported.
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* @rcv_sel_bit: Receiver select bit. 0 if unsupported.
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* @drv_reg: Drive fields register offset. -1 if unsupported.
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* This register contains the hsm, schmitt, lpmd, drvdn,
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* drvup, slwr, and slwf parameters.
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@ -110,6 +117,9 @@ struct tegra_function {
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* @slwr_width: Slew Rising field width. 0 if unsupported.
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* @slwf_bit: Slew Falling register bit. 0 if unsupported.
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* @slwf_width: Slew Falling field width. 0 if unsupported.
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* @drvtype_reg: Drive type fields register offset. -1 if unsupported.
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* @drvtype_bank: Drive type fields register bank. 0 if unsupported.
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* @drvtype_bit: Drive type register bit. 0 if unsupported.
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*
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* A representation of a group of pins (possibly just one pin) in the Tegra
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* pin controller. Each group allows some parameter or parameters to be
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@ -131,15 +141,19 @@ struct tegra_pingroup {
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s16 odrain_reg;
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s16 lock_reg;
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s16 ioreset_reg;
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s16 rcv_sel_reg;
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s16 drv_reg;
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s16 drvtype_reg;
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u32 mux_bank:2;
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u32 pupd_bank:2;
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u32 tri_bank:2;
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u32 einput_bank:2;
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u32 odrain_bank:2;
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u32 ioreset_bank:2;
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u32 rcv_sel_bank:2;
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u32 lock_bank:2;
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u32 drv_bank:2;
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u32 drvtype_bank:2;
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u32 mux_bit:5;
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u32 pupd_bit:5;
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u32 tri_bit:5;
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@ -147,6 +161,7 @@ struct tegra_pingroup {
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u32 odrain_bit:5;
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u32 lock_bit:5;
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u32 ioreset_bit:5;
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u32 rcv_sel_bit:5;
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u32 hsm_bit:5;
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u32 schmitt_bit:5;
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u32 lpmd_bit:5;
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@ -154,6 +169,7 @@ struct tegra_pingroup {
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u32 drvup_bit:5;
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u32 slwr_bit:5;
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u32 slwf_bit:5;
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u32 drvtype_bit:5;
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u32 drvdn_width:6;
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u32 drvup_width:6;
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u32 slwr_width:6;
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@ -2624,7 +2624,9 @@ static const struct tegra_function tegra20_functions[] = {
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.odrain_reg = -1, \
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.lock_reg = -1, \
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.ioreset_reg = -1, \
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.rcv_sel_reg = -1, \
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.drv_reg = -1, \
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.drvtype_reg = -1, \
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}
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/* Pin groups with only pull up and pull down control */
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@ -2642,7 +2644,9 @@ static const struct tegra_function tegra20_functions[] = {
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.odrain_reg = -1, \
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.lock_reg = -1, \
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.ioreset_reg = -1, \
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.rcv_sel_reg = -1, \
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.drv_reg = -1, \
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.drvtype_reg = -1, \
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}
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/* Pin groups for drive strength registers (configurable version) */
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@ -2660,6 +2664,7 @@ static const struct tegra_function tegra20_functions[] = {
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.odrain_reg = -1, \
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.lock_reg = -1, \
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.ioreset_reg = -1, \
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.rcv_sel_reg = -1, \
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.drv_reg = ((r) - PINGROUP_REG_A), \
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.drv_bank = 3, \
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.hsm_bit = hsm_b, \
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@ -2673,6 +2678,7 @@ static const struct tegra_function tegra20_functions[] = {
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.slwr_width = slwr_w, \
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.slwf_bit = slwf_b, \
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.slwf_width = slwf_w, \
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.drvtype_reg = -1, \
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}
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/* Pin groups for drive strength registers (simple version) */
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@ -3384,7 +3384,9 @@ static const struct tegra_function tegra30_functions[] = {
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.ioreset_reg = PINGROUP_REG_##ior(r), \
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.ioreset_bank = 1, \
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.ioreset_bit = 8, \
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.rcv_sel_reg = -1, \
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.drv_reg = -1, \
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.drvtype_reg = -1, \
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}
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#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
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@ -3401,6 +3403,7 @@ static const struct tegra_function tegra30_functions[] = {
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.odrain_reg = -1, \
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.lock_reg = -1, \
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.ioreset_reg = -1, \
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.rcv_sel_reg = -1, \
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.drv_reg = ((r) - DRV_PINGROUP_REG_A), \
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.drv_bank = 0, \
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.hsm_bit = hsm_b, \
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@ -3414,6 +3417,7 @@ static const struct tegra_function tegra30_functions[] = {
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.slwr_width = slwr_w, \
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.slwf_bit = slwf_b, \
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.slwf_width = slwf_w, \
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.drvtype_reg = -1, \
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}
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static const struct tegra_pingroup tegra30_groups[] = {
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