gpio: pl061: convert to use generic irq chip
Convert the pl061 irq_chip code to use the generic irq chip code. This has the side effect of using 32-bit accesses rather than 8-bit accesses to interrupt registers. The h/w TRM and testing seem to indicate this is fine. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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2b84112718
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3ab5247544
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@ -138,6 +138,7 @@ config GPIO_MXS
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config GPIO_PL061
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bool "PrimeCell PL061 GPIO support"
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depends on ARM_AMBA
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select GENERIC_IRQ_CHIP
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help
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Say yes here to support the PrimeCell PL061 GPIO device
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@ -50,10 +50,10 @@ struct pl061_gpio {
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* the IRQ code simpler.
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*/
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spinlock_t lock; /* GPIO registers */
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spinlock_t irq_lock; /* IRQ registers */
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void __iomem *base;
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int irq_base;
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struct irq_chip_generic *irq_gc;
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struct gpio_chip gc;
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};
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@ -125,40 +125,10 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
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return chip->irq_base + offset;
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}
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/*
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* PL061 GPIO IRQ
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*/
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static void pl061_irq_disable(struct irq_data *d)
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{
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struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
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int offset = d->irq - chip->irq_base;
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unsigned long flags;
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u8 gpioie;
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spin_lock_irqsave(&chip->irq_lock, flags);
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gpioie = readb(chip->base + GPIOIE);
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gpioie &= ~(1 << offset);
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writeb(gpioie, chip->base + GPIOIE);
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spin_unlock_irqrestore(&chip->irq_lock, flags);
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}
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static void pl061_irq_enable(struct irq_data *d)
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{
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struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
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int offset = d->irq - chip->irq_base;
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unsigned long flags;
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u8 gpioie;
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spin_lock_irqsave(&chip->irq_lock, flags);
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gpioie = readb(chip->base + GPIOIE);
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gpioie |= 1 << offset;
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writeb(gpioie, chip->base + GPIOIE);
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spin_unlock_irqrestore(&chip->irq_lock, flags);
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}
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static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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{
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struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pl061_gpio *chip = gc->private;
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int offset = d->irq - chip->irq_base;
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unsigned long flags;
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u8 gpiois, gpioibe, gpioiev;
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@ -166,7 +136,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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if (offset < 0 || offset >= PL061_GPIO_NR)
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return -EINVAL;
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spin_lock_irqsave(&chip->irq_lock, flags);
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raw_spin_lock_irqsave(&gc->lock, flags);
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gpioiev = readb(chip->base + GPIOIEV);
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@ -195,18 +165,11 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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writeb(gpioiev, chip->base + GPIOIEV);
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spin_unlock_irqrestore(&chip->irq_lock, flags);
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raw_spin_unlock_irqrestore(&gc->lock, flags);
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return 0;
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}
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static struct irq_chip pl061_irqchip = {
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.name = "GPIO",
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.irq_enable = pl061_irq_enable,
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.irq_disable = pl061_irq_disable,
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.irq_set_type = pl061_irq_type,
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};
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static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct list_head *chip_list = irq_get_handler_data(irq);
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@ -232,6 +195,25 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
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chained_irq_exit(irqchip, desc);
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}
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static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
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{
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struct irq_chip_type *ct;
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chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
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chip->base, handle_simple_irq);
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chip->irq_gc->private = chip;
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ct = chip->irq_gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = pl061_irq_type;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->regs.mask = GPIOIE;
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irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
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IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
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}
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static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
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{
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struct pl061_platform_data *pdata;
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@ -269,7 +251,6 @@ static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
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}
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spin_lock_init(&chip->lock);
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spin_lock_init(&chip->irq_lock);
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INIT_LIST_HEAD(&chip->list);
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chip->gc.direction_input = pl061_direction_input;
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@ -293,6 +274,8 @@ static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
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if (chip->irq_base <= 0)
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return 0;
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pl061_init_gc(chip, chip->irq_base);
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writeb(0, chip->base + GPIOIE); /* disable irqs */
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irq = dev->irq[0];
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if (irq < 0) {
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@ -321,11 +304,6 @@ static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
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else
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pl061_direction_input(&chip->gc, i);
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}
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irq_set_chip_and_handler(i + chip->irq_base, &pl061_irqchip,
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handle_simple_irq);
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set_irq_flags(i+chip->irq_base, IRQF_VALID);
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irq_set_chip_data(i + chip->irq_base, chip);
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}
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return 0;
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