sh: Setup early PMB mappings.
More and more boards are going to start shipping that boot with the MMU in 32BIT mode by default. Previously we relied on the bootloader to setup PMB mappings for use by the kernel but we also need to cater for boards whose bootloaders don't set them up. If CONFIG_PMB_LEGACY is not enabled we have full control over our PMB mappings and can compress our address space. Usually, the distance between the the cached and uncached mappings of RAM is always 512MB, however we can compress the distance to be the amount of RAM on the board. pmb_init() now becomes much simpler. It no longer has to calculate any mappings, it just has to synchronise the software PMB table with the hardware. Tested on SDK7786 and SH7785LCR. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Matt Fleming
Paul Mundt
parent
7dcaa8e8e6
commit
3d467676ab
@ -3,6 +3,7 @@
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* arch/sh/kernel/head.S
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
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* Copyright (C) 2010 Matt Fleming
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -84,6 +85,236 @@ ENTRY(_stext)
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ldc r0, r7_bank ! ... and initial thread_info
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#endif
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#if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
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/*
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* Reconfigure the initial PMB mappings setup by the hardware.
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*
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* When we boot in 32-bit MMU mode there are 2 PMB entries already
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* setup for us.
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*
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* Entry VPN PPN V SZ C UB WT
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* ---------------------------------------------------------------
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* 0 0x80000000 0x00000000 1 512MB 1 0 1
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* 1 0xA0000000 0x00000000 1 512MB 0 0 0
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*
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* But we reprogram them here because we want complete control over
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* our address space and the initial mappings may not map PAGE_OFFSET
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* to __MEMORY_START (or even map all of our RAM).
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*
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* Once we've setup cached and uncached mappings for all of RAM we
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* clear the rest of the PMB entries.
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*
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* This clearing also deals with the fact that PMB entries can persist
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* across reboots. The PMB could have been left in any state when the
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* reboot occurred, so to be safe we clear all entries and start with
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* with a clean slate.
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*/
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mov.l .LMMUCR, r1 /* Flush the TLB */
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mov.l @r1, r0
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or #MMUCR_TI, r0
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mov.l r0, @r1
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mov.l .LMEMORY_SIZE, r5
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mov r5, r7
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mov #PMB_E_SHIFT, r0
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mov #0x1, r4
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shld r0, r4
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mov.l .LFIRST_DATA_ENTRY, r0
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mov.l .LPMB_DATA, r1
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mov.l .LFIRST_ADDR_ENTRY, r2
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mov.l .LPMB_ADDR, r3
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mov #0, r10
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/*
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* r0 = PMB_DATA data field
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* r1 = PMB_DATA address field
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* r2 = PMB_ADDR data field
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* r3 = PMB_ADDR address field
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* r4 = PMB_E_SHIFT
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* r5 = remaining amount of RAM to map
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* r6 = PMB mapping size we're trying to use
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* r7 = cached_to_uncached
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* r8 = scratch register
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* r9 = scratch register
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* r10 = number of PMB entries we've setup
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*/
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.L512:
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mov #(512 >> 4), r6
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shll16 r6
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shll8 r6
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cmp/hi r5, r6
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bt .L128
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mov #(PMB_SZ_512M >> 2), r9
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shll2 r9
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/*
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* Cached mapping
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*/
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mov #PMB_C, r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov.l r2, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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/*
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* Uncached mapping
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*/
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mov #(PMB_UB >> 8), r8
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shll8 r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov r2, r8
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add r7, r8
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mov.l r8, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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sub r6, r5
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add r6, r0
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add r6, r2
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bra .L512
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.L128:
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mov #(128 >> 4), r6
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shll16 r6
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shll8 r6
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cmp/hi r5, r6
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bt .L64
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mov #(PMB_SZ_128M >> 2), r9
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shll2 r9
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/*
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* Cached mapping
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*/
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mov #PMB_C, r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov.l r2, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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/*
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* Uncached mapping
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*/
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mov #(PMB_UB >> 8), r8
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shll8 r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov r2, r8
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add r7, r8
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mov.l r8, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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sub r6, r5
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add r6, r0
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add r6, r2
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bra .L128
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.L64:
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mov #(64 >> 4), r6
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shll16 r6
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shll8 r6
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cmp/hi r5, r6
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bt .Ldone
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mov #(PMB_SZ_64M >> 2), r9
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shll2 r9
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/*
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* Cached mapping
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*/
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mov #PMB_C, r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov.l r2, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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/*
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* Uncached mapping
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*/
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mov #(PMB_UB >> 8), r8
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shll8 r8
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or r0, r8
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or r9, r8
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mov.l r8, @r1
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mov r2, r8
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add r7, r8
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mov.l r8, @r3
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add r4, r1 /* Increment to the next PMB_DATA entry */
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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add #1, r10 /* Increment number of PMB entries */
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sub r6, r5
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add r6, r0
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add r6, r2
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bra .L64
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.Ldone:
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/* Update cached_to_uncached */
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mov.l .Lcached_to_uncached, r0
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mov.l r7, @r0
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/*
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* Clear the remaining PMB entries.
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*
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* r3 = entry to begin clearing from
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* r10 = number of entries we've setup so far
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*/
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mov #0, r1
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mov #PMB_ENTRY_MAX, r0
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.Lagain:
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mov.l r1, @r3 /* Clear PMB_ADDR entry */
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add #1, r10 /* Increment the loop counter */
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cmp/eq r0, r10
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bf/s .Lagain
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add r4, r3 /* Increment to the next PMB_ADDR entry */
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mov.l 6f, r0
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icbi @r0
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#endif /* !CONFIG_PMB_LEGACY */
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#ifndef CONFIG_SH_NO_BSS_INIT
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/*
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* Don't clear BSS if running on slow platforms such as an RTL simulation,
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@ -133,3 +364,13 @@ ENTRY(stack_start)
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5: .long start_kernel
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6: .long sh_cpu_init
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7: .long init_thread_union
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#if defined(CONFIG_PMB) && !defined(CONFIG_PMB_LEGACY)
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.LPMB_ADDR: .long PMB_ADDR
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.LPMB_DATA: .long PMB_DATA
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.LFIRST_ADDR_ENTRY: .long PAGE_OFFSET | PMB_V
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.LFIRST_DATA_ENTRY: .long __MEMORY_START | PMB_V
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.LMMUCR: .long MMUCR
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.Lcached_to_uncached: .long cached_to_uncached
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.LMEMORY_SIZE: .long __MEMORY_SIZE
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#endif
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166
arch/sh/mm/pmb.c
166
arch/sh/mm/pmb.c
@ -3,11 +3,8 @@
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*
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* Privileged Space Mapping Buffer (PMB) Support.
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*
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* Copyright (C) 2005 - 2010 Paul Mundt
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*
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* P1/P2 Section mapping definitions from map32.h, which was:
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*
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* Copyright 2003 (c) Lineo Solutions,Inc.
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* Copyright (C) 2005 - 2010 Paul Mundt
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* Copyright (C) 2010 Matt Fleming
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -280,12 +277,119 @@ static void __pmb_unmap(struct pmb_entry *pmbe)
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}
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#ifdef CONFIG_PMB_LEGACY
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static inline unsigned int pmb_ppn_in_range(unsigned long ppn)
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{
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return ppn >= __MEMORY_START && ppn < __MEMORY_START + __MEMORY_SIZE;
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}
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static int pmb_apply_legacy_mappings(void)
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{
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unsigned int applied = 0;
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int i;
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pr_info("PMB: Preserving legacy mappings:\n");
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/*
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* The following entries are setup by the bootloader.
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*
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* Entry VPN PPN V SZ C UB
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* --------------------------------------------------------
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* 0 0xA0000000 0x00000000 1 64MB 0 0
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* 1 0xA4000000 0x04000000 1 16MB 0 0
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* 2 0xA6000000 0x08000000 1 16MB 0 0
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* 9 0x88000000 0x48000000 1 128MB 1 1
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* 10 0x90000000 0x50000000 1 128MB 1 1
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* 11 0x98000000 0x58000000 1 128MB 1 1
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* 13 0xA8000000 0x48000000 1 128MB 0 0
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* 14 0xB0000000 0x50000000 1 128MB 0 0
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* 15 0xB8000000 0x58000000 1 128MB 0 0
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*
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* The only entries the we need are the ones that map the kernel
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* at the cached and uncached addresses.
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*/
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for (i = 0; i < PMB_ENTRY_MAX; i++) {
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unsigned long addr, data;
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unsigned long addr_val, data_val;
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unsigned long ppn, vpn;
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addr = mk_pmb_addr(i);
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data = mk_pmb_data(i);
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addr_val = __raw_readl(addr);
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data_val = __raw_readl(data);
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/*
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* Skip over any bogus entries
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*/
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if (!(data_val & PMB_V) || !(addr_val & PMB_V))
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continue;
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ppn = data_val & PMB_PFN_MASK;
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vpn = addr_val & PMB_PFN_MASK;
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/*
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* Only preserve in-range mappings.
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*/
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if (pmb_ppn_in_range(ppn)) {
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unsigned int size;
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char *sz_str = NULL;
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size = data_val & PMB_SZ_MASK;
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sz_str = (size == PMB_SZ_16M) ? " 16MB":
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(size == PMB_SZ_64M) ? " 64MB":
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(size == PMB_SZ_128M) ? "128MB":
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"512MB";
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pr_info("\t0x%08lx -> 0x%08lx [ %s %scached ]\n",
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vpn >> PAGE_SHIFT, ppn >> PAGE_SHIFT, sz_str,
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(data_val & PMB_C) ? "" : "un");
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applied++;
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} else {
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/*
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* Invalidate anything out of bounds.
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*/
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__raw_writel(addr_val & ~PMB_V, addr);
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__raw_writel(data_val & ~PMB_V, data);
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}
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}
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return (applied == 0);
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}
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#else
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static inline int pmb_apply_legacy_mappings(void)
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{
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return 1;
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}
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#endif
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int __uses_jump_to_uncached pmb_init(void)
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{
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int i;
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unsigned long addr, data;
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unsigned int applied = 0;
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unsigned long ret;
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jump_to_uncached();
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/*
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* Attempt to apply the legacy boot mappings if configured. If
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* this is successful then we simply carry on with those and
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* don't bother establishing additional memory mappings. Dynamic
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* device mappings through pmb_remap() can still be bolted on
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* after this.
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*/
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ret = pmb_apply_legacy_mappings();
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if (ret == 0) {
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back_to_cached();
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return 0;
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}
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/*
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* Sync our software copy of the PMB mappings with those in
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* hardware. The mappings in the hardware PMB were either set up
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* by the bootloader or very early on by the kernel.
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*/
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for (i = 0; i < PMB_ENTRY_MAX; i++) {
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struct pmb_entry *pmbe;
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unsigned long vpn, ppn, flags;
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@ -318,60 +422,10 @@ static int pmb_apply_legacy_mappings(void)
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pmbe = pmb_alloc(vpn, ppn, flags, i);
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WARN_ON(IS_ERR(pmbe));
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applied++;
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}
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return (applied == 0);
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}
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#else
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static inline int pmb_apply_legacy_mappings(void)
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{
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return 1;
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}
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#endif
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int __uses_jump_to_uncached pmb_init(void)
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{
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unsigned int i;
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unsigned long size, ret;
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jump_to_uncached();
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/*
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* Attempt to apply the legacy boot mappings if configured. If
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* this is successful then we simply carry on with those and
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* don't bother establishing additional memory mappings. Dynamic
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* device mappings through pmb_remap() can still be bolted on
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* after this.
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*/
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ret = pmb_apply_legacy_mappings();
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if (ret == 0) {
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back_to_cached();
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return 0;
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}
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/*
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* Insert PMB entries for the P1 and P2 areas so that, after
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* we've switched the MMU to 32-bit mode, the semantics of P1
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* and P2 are the same as in 29-bit mode, e.g.
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*
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* P1 - provides a cached window onto physical memory
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* P2 - provides an uncached window onto physical memory
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*/
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size = (unsigned long)__MEMORY_START + __MEMORY_SIZE;
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ret = pmb_remap(P1SEG, 0x00000000, size, PMB_C);
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BUG_ON(ret != size);
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ret = pmb_remap(P2SEG, 0x00000000, size, PMB_WT | PMB_UB);
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BUG_ON(ret != size);
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ctrl_outl(0, PMB_IRMCR);
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/* PMB.SE and UB[7] */
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ctrl_outl(PASCR_SE | (1 << 7), PMB_PASCR);
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/* Flush out the TLB */
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i = ctrl_inl(MMUCR);
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i |= MMUCR_TI;
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