Blackfin: add ICPLB coverage for async banks
When doing XIP, we need to execute out of the async banks, so we need ICPLBs to allow this. Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -36,7 +36,7 @@ int first_switched_icplb PDT_ATTR;
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int first_switched_dcplb PDT_ATTR;
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struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
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struct cplb_boundary icplb_bounds[7] PDT_ATTR;
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struct cplb_boundary icplb_bounds[9] PDT_ATTR;
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int icplb_nr_bounds PDT_ATTR;
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int dcplb_nr_bounds PDT_ATTR;
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@ -167,14 +167,21 @@ void __init generate_cplb_tables_all(void)
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icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
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SDRAM_IGENERIC : SDRAM_INON_CHBL);
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}
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/* Addressing hole up to the async bank. */
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icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
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icplb_bounds[i_i++].data = 0;
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/* ASYNC banks. */
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icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
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icplb_bounds[i_i++].data = SDRAM_EBIU;
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/* Addressing hole up to BootROM. */
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icplb_bounds[i_i].eaddr = BOOT_ROM_START;
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icplb_bounds[i_i++].data = 0;
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/* BootROM -- largest one should be less than 1 meg. */
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icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
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icplb_bounds[i_i++].data = SDRAM_IGENERIC;
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if (L2_LENGTH) {
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/* Addressing hole up to L2 SRAM, including the async bank. */
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/* Addressing hole up to L2 SRAM. */
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icplb_bounds[i_i].eaddr = L2_START;
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icplb_bounds[i_i++].data = 0;
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/* L2 SRAM. */
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