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chelsio: use C99 style initialization

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Convert some initialized structures to C99 style.

Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger 2007-02-20 15:58:01 -08:00 committed by Jeff Garzik
parent 4d2b8f66b8
commit 4c247db114
1 changed files with 130 additions and 57 deletions
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187
drivers/net/chelsio/subr.c
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@ -322,9 +322,9 @@ static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
#if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR) #if defined(CONFIG_CHELSIO_T1_1G) || defined(CONFIG_CHELSIO_T1_COUGAR)
static struct mdio_ops mi1_mdio_ops = { static struct mdio_ops mi1_mdio_ops = {
mi1_mdio_init, .init = mi1_mdio_init,
mi1_mdio_read, .read = mi1_mdio_read,
mi1_mdio_write .write = mi1_mdio_write
}; };
#endif #endif
@ -378,9 +378,9 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
} }
static struct mdio_ops mi1_mdio_ext_ops = { static struct mdio_ops mi1_mdio_ext_ops = {
mi1_mdio_init, .init = mi1_mdio_init,
mi1_mdio_ext_read, .read = mi1_mdio_ext_read,
mi1_mdio_ext_write .write = mi1_mdio_ext_write
}; };
enum { enum {
@ -392,63 +392,136 @@ enum {
CH_BRD_N204_4CU, CH_BRD_N204_4CU,
}; };
static struct board_info t1_board[] = { static const struct board_info t1_board[] = {
{
.board = CHBT_BOARD_CHT110,
.port_number = 1,
.caps = SUPPORTED_10000baseT_Full,
.chip_term = CHBT_TERM_T1,
.chip_mac = CHBT_MAC_PM3393,
.chip_phy = CHBT_PHY_MY3126,
.clock_core = 125000000,
.clock_mc3 = 150000000,
.clock_mc4 = 125000000,
.espi_nports = 1,
.clock_elmer0 = 44,
.mdio_mdien = 1,
.mdio_mdiinv = 1,
.mdio_mdc = 1,
.mdio_phybaseaddr = 1,
.gmac = &t1_pm3393_ops,
.gphy = &t1_my3126_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio T110 1x10GBase-CX4 TOE",
},
{ CHBT_BOARD_CHT110, 1/*ports#*/, {
SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1, .board = CHBT_BOARD_N110,
CHBT_MAC_PM3393, CHBT_PHY_MY3126, .port_number = 1,
125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/, .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/, .chip_term = CHBT_TERM_T1,
1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops, .chip_mac = CHBT_MAC_PM3393,
&t1_my3126_ops, &mi1_mdio_ext_ops, .chip_phy = CHBT_PHY_88X2010,
"Chelsio T110 1x10GBase-CX4 TOE" }, .clock_core = 125000000,
.espi_nports = 1,
.clock_elmer0 = 44,
.mdio_mdien = 0,
.mdio_mdiinv = 0,
.mdio_mdc = 1,
.mdio_phybaseaddr = 0,
.gmac = &t1_pm3393_ops,
.gphy = &t1_mv88x201x_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio N110 1x10GBaseX NIC",
},
{ CHBT_BOARD_N110, 1/*ports#*/, {
SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1, .board = CHBT_BOARD_N210,
CHBT_MAC_PM3393, CHBT_PHY_88X2010, .port_number = 1,
125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/, .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/, .chip_term = CHBT_TERM_T2,
0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops, .chip_mac = CHBT_MAC_PM3393,
&t1_mv88x201x_ops, &mi1_mdio_ext_ops, .chip_phy = CHBT_PHY_88X2010,
"Chelsio N110 1x10GBaseX NIC" }, .clock_core = 125000000,
.espi_nports = 1,
.clock_elmer0 = 44,
.mdio_mdien = 0,
.mdio_mdiinv = 0,
.mdio_mdc = 1,
.mdio_phybaseaddr = 0,
.gmac = &t1_pm3393_ops,
.gphy = &t1_mv88x201x_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio N210 1x10GBaseX NIC",
},
{ CHBT_BOARD_N210, 1/*ports#*/, {
SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T2, .board = CHBT_BOARD_CHT210,
CHBT_MAC_PM3393, CHBT_PHY_88X2010, .port_number = 1,
125000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/, .caps = SUPPORTED_10000baseT_Full,
1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/, .chip_term = CHBT_TERM_T2,
0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops, .chip_mac = CHBT_MAC_PM3393,
&t1_mv88x201x_ops, &mi1_mdio_ext_ops, .chip_phy = CHBT_PHY_88X2010,
"Chelsio N210 1x10GBaseX NIC" }, .clock_core = 125000000,
.clock_mc3 = 133000000,
.clock_mc4 = 125000000,
.espi_nports = 1,
.clock_elmer0 = 44,
.mdio_mdien = 0,
.mdio_mdiinv = 0,
.mdio_mdc = 1,
.mdio_phybaseaddr = 0,
.gmac = &t1_pm3393_ops,
.gphy = &t1_mv88x201x_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio T210 1x10GBaseX TOE",
},
{ CHBT_BOARD_CHT210, 1/*ports#*/, {
SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2, .board = CHBT_BOARD_CHT210,
CHBT_MAC_PM3393, CHBT_PHY_88X2010, .port_number = 1,
125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/, .caps = SUPPORTED_10000baseT_Full,
1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/, .chip_term = CHBT_TERM_T2,
0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops, .chip_mac = CHBT_MAC_PM3393,
&t1_mv88x201x_ops, &mi1_mdio_ext_ops, .chip_phy = CHBT_PHY_MY3126,
"Chelsio T210 1x10GBaseX TOE" }, .clock_core = 125000000,
.clock_mc3 = 133000000,
{ CHBT_BOARD_CHT210, 1/*ports#*/, .clock_mc4 = 125000000,
SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2, .espi_nports = 1,
CHBT_MAC_PM3393, CHBT_PHY_MY3126, .clock_elmer0 = 44,
125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/, .mdio_mdien = 1,
1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/, .mdio_mdiinv = 1,
1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops, .mdio_mdc = 1,
&t1_my3126_ops, &mi1_mdio_ext_ops, .mdio_phybaseaddr = 1,
"Chelsio T210 1x10GBase-CX4 TOE" }, .gmac = &t1_pm3393_ops,
.gphy = &t1_my3126_ops,
.mdio_ops = &mi1_mdio_ext_ops,
.desc = "Chelsio T210 1x10GBase-CX4 TOE",
},
#ifdef CONFIG_CHELSIO_T1_1G #ifdef CONFIG_CHELSIO_T1_1G
{ CHBT_BOARD_CHN204, 4/*ports#*/, {
SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | .board = CHBT_BOARD_CHN204,
SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | .port_number = 4,
SUPPORTED_PAUSE | SUPPORTED_TP /*caps*/, CHBT_TERM_T2, CHBT_MAC_VSC7321, CHBT_PHY_88E1111, .caps = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
100000000/*clk-core*/, 0/*clk-mc3*/, 0/*clk-mc4*/, | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
4/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/, | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
0/*mdiinv*/, 1/*mdc*/, 4/*phybaseaddr*/, &t1_vsc7326_ops, SUPPORTED_PAUSE | SUPPORTED_TP,
&t1_mv88e1xxx_ops, &mi1_mdio_ops, .chip_term = CHBT_TERM_T2,
"Chelsio N204 4x100/1000BaseT NIC" }, .chip_mac = CHBT_MAC_VSC7321,
.chip_phy = CHBT_PHY_88E1111,
.clock_core = 100000000,
.espi_nports = 4,
.clock_elmer0 = 44,
.mdio_mdien = 0,
.mdio_mdiinv = 0,
.mdio_mdc = 0,
.mdio_phybaseaddr = 4,
.gmac = &t1_vsc7326_ops,
.gphy = &t1_mv88e1xxx_ops,
.mdio_ops = &mi1_mdio_ops,
.desc = "Chelsio N204 4x100/1000BaseT NIC",
},
#endif #endif
}; };