sh: Add support for R7780RP and R7780MP boards.
This adds support for the Renesas SH7780 development boards, R7780RP and R7780MP. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
d7c30c682a
commit
5283ecb5cc
@ -404,6 +404,8 @@ source "arch/sh/boards/renesas/hs7751rvoip/Kconfig"
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source "arch/sh/boards/renesas/rts7751r2d/Kconfig"
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source "arch/sh/boards/renesas/r7780rp/Kconfig"
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config SH_PCLK_FREQ
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int "Peripheral clock frequency (in Hz)"
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default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780
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@ -104,6 +104,7 @@ machdir-$(CONFIG_SH_HS7751RVOIP) := renesas/hs7751rvoip
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machdir-$(CONFIG_SH_RTS7751R2D) := renesas/rts7751r2d
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machdir-$(CONFIG_SH_7751_SYSTEMH) := renesas/systemh
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machdir-$(CONFIG_SH_EDOSK7705) := renesas/edosk7705
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machdir-$(CONFIG_SH_R7780RP) := renesas/r7780rp
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machdir-$(CONFIG_SH_SH4202_MICRODEV) := superh/microdev
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machdir-$(CONFIG_SH_LANDISK) := landisk
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machdir-$(CONFIG_SH_TITAN) := titan
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14
arch/sh/boards/renesas/r7780rp/Kconfig
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14
arch/sh/boards/renesas/r7780rp/Kconfig
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@ -0,0 +1,14 @@
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if SH_R7780RP
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menu "R7780RP options"
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config SH_R7780MP
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bool "R7780MP board support"
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default y
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help
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Selecting this option will enable support for the mass-production
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version of the R7780RP. If in doubt, say Y.
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endmenu
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endif
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6
arch/sh/boards/renesas/r7780rp/Makefile
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6
arch/sh/boards/renesas/r7780rp/Makefile
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@ -0,0 +1,6 @@
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#
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# Makefile for the R7780RP-1 specific parts of the kernel
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#
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obj-y := setup.o io.o irq.o
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obj-$(CONFIG_HEARTBEAT) += led.o
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338
arch/sh/boards/renesas/r7780rp/io.c
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338
arch/sh/boards/renesas/r7780rp/io.c
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@ -0,0 +1,338 @@
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/*
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* linux/arch/sh/kernel/io_r7780rp.c
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*
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* Copyright (C) 2001 Ian da Silva, Jeremy Siegel
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* Based largely on io_se.c.
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*
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* I/O routine for Renesas Solutions Highlander R7780RP-1
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*
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* Initial version only to support LAN access; some
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* placeholder code from io_r7780rp.c left in with the
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* expectation of later SuperIO and PCMCIA access.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/r7780rp/r7780rp.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include "../../../drivers/pci/pci-sh7780.h"
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/*
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* The 7780 R7780RP-1 uses the built-in PCI controller (PCIC)
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* of the 7780 processor, and has a SuperIO accessible via the PCI.
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* The board also includes a PCMCIA controller on its memory bus,
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* like the other Solution Engine boards.
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*/
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#define SH7780_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
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#define PCIIOBR (volatile long *)PCI_REG(SH7780_PCIIOBR)
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#define PCIMBR (volatile long *)PCI_REG(SH7780_PCIMBR)
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#define PCI_IO_AREA SH7780_PCI_IO_BASE
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#define PCI_MEM_AREA SH7780_PCI_CONFIG_BASE
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#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7780_PCIIOBR_MASK))
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static inline void delay(void)
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{
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ctrl_inw(0xa0000000);
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}
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static inline unsigned long port2adr(unsigned int port)
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{
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if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
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if (port == 0x3f6)
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return (PA_AREA5_IO + 0x80c);
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else
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return (PA_AREA5_IO + 0x1000 + ((port-0x1f0) << 1));
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else
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maybebadio((unsigned long)port);
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return port;
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}
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static inline unsigned long port88796l(unsigned int port, int flag)
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{
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unsigned long addr;
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if (flag)
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addr = PA_AX88796L + ((port - AX88796L_IO_BASE) << 1);
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else
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addr = PA_AX88796L + ((port - AX88796L_IO_BASE) << 1) + 0x1000;
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return addr;
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}
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/* The 7780 R7780RP-1 seems to have everything hooked */
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/* up pretty normally (nothing on high-bytes only...) so this */
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/* shouldn't be needed */
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static inline int shifted_port(unsigned long port)
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{
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/* For IDE registers, value is not shifted */
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if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
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return 0;
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else
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return 1;
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}
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/* In case someone configures the kernel w/o PCI support: in that */
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/* scenario, don't ever bother to check for PCI-window addresses */
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/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */
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#if defined(CONFIG_PCI)
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#define CHECK_SH7780_PCIIO(port) \
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((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7780_PCI_IO_SIZE)))
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#else
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#define CHECK_SH7780_PCIIO(port) (0)
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#endif
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#if defined(CONFIG_NE2000) || defined(CONFIG_NE2000_MODULE)
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#define CHECK_AX88796L_PORT(port) \
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((port >= AX88796L_IO_BASE) && (port < (AX88796L_IO_BASE+0x20)))
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#else
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#define CHECK_AX88796L_PORT(port) (0)
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#endif
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/*
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* General outline: remap really low stuff [eventually] to SuperIO,
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* stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
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* is mapped through the PCI IO window. Stuff with high bits (PXSEG)
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* should be way beyond the window, and is used w/o translation for
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* compatibility.
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*/
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u8 r7780rp_inb(unsigned long port)
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{
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if (CHECK_AX88796L_PORT(port))
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return ctrl_inw(port88796l(port, 0)) & 0xff;
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else if (PXSEG(port))
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return ctrl_inb(port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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return ctrl_inb(PCI_IOMAP(port));
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return ctrl_inw(port2adr(port)) & 0xff;
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}
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u8 r7780rp_inb_p(unsigned long port)
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{
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u8 v;
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if (CHECK_AX88796L_PORT(port))
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v = ctrl_inw(port88796l(port, 0)) & 0xff;
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else if (PXSEG(port))
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v = ctrl_inb(port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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v = ctrl_inb(PCI_IOMAP(port));
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else
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v = ctrl_inw(port2adr(port)) & 0xff;
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delay();
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return v;
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}
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u16 r7780rp_inw(unsigned long port)
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{
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if (CHECK_AX88796L_PORT(port))
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maybebadio(port);
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else if (PXSEG(port))
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return ctrl_inw(port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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return ctrl_inw(PCI_IOMAP(port));
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else
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maybebadio(port);
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return 0;
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}
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u32 r7780rp_inl(unsigned long port)
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{
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if (CHECK_AX88796L_PORT(port))
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maybebadio(port);
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else if (PXSEG(port))
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return ctrl_inl(port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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return ctrl_inl(PCI_IOMAP(port));
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else
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maybebadio(port);
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return 0;
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}
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void r7780rp_outb(u8 value, unsigned long port)
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{
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if (CHECK_AX88796L_PORT(port))
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ctrl_outw(value, port88796l(port, 0));
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else if (PXSEG(port))
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ctrl_outb(value, port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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ctrl_outb(value, PCI_IOMAP(port));
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else
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ctrl_outw(value, port2adr(port));
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}
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void r7780rp_outb_p(u8 value, unsigned long port)
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{
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if (CHECK_AX88796L_PORT(port))
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ctrl_outw(value, port88796l(port, 0));
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else if (PXSEG(port))
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ctrl_outb(value, port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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ctrl_outb(value, PCI_IOMAP(port));
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else
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ctrl_outw(value, port2adr(port));
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delay();
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}
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void r7780rp_outw(u16 value, unsigned long port)
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{
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if (CHECK_AX88796L_PORT(port))
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maybebadio(port);
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else if (PXSEG(port))
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ctrl_outw(value, port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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ctrl_outw(value, PCI_IOMAP(port));
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else
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maybebadio(port);
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}
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void r7780rp_outl(u32 value, unsigned long port)
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{
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if (CHECK_AX88796L_PORT(port))
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maybebadio(port);
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else if (PXSEG(port))
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ctrl_outl(value, port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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ctrl_outl(value, PCI_IOMAP(port));
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else
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maybebadio(port);
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}
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void r7780rp_insb(unsigned long port, void *dst, unsigned long count)
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{
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volatile u16 *p;
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u8 *buf = dst;
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if (CHECK_AX88796L_PORT(port)) {
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p = (volatile u16 *)port88796l(port, 0);
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while (count--)
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*buf++ = *p & 0xff;
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} else if (PXSEG(port)) {
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while (count--)
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*buf++ = *(volatile u8 *)port;
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} else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
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volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
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while (count--)
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*buf++ = *bp;
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} else {
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p = (volatile u16 *)port2adr(port);
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while (count--)
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*buf++ = *p & 0xff;
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}
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}
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void r7780rp_insw(unsigned long port, void *dst, unsigned long count)
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{
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volatile u16 *p;
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u16 *buf = dst;
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if (CHECK_AX88796L_PORT(port))
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p = (volatile u16 *)port88796l(port, 1);
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else if (PXSEG(port))
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p = (volatile u16 *)port;
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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p = (volatile u16 *)PCI_IOMAP(port);
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else
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p = (volatile u16 *)port2adr(port);
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while (count--)
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*buf++ = *p;
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}
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void r7780rp_insl(unsigned long port, void *dst, unsigned long count)
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{
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u32 *buf = dst;
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if (CHECK_AX88796L_PORT(port))
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maybebadio(port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
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volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
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while (count--)
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*buf++ = *p;
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} else
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maybebadio(port);
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}
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void r7780rp_outsb(unsigned long port, const void *src, unsigned long count)
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{
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volatile u16 *p;
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const u8 *buf = src;
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if (CHECK_AX88796L_PORT(port)) {
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p = (volatile u16 *)port88796l(port, 0);
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while (count--)
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*p = *buf++;
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} else if (PXSEG(port))
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while (count--)
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ctrl_outb(*buf++, port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
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volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);
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while (count--)
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*bp = *buf++;
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} else {
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p = (volatile u16 *)port2adr(port);
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while (count--)
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*p = *buf++;
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}
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}
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void r7780rp_outsw(unsigned long port, const void *src, unsigned long count)
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{
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volatile u16 *p;
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const u16 *buf = src;
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if (CHECK_AX88796L_PORT(port))
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p = (volatile u16 *)port88796l(port, 1);
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else if (PXSEG(port))
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p = (volatile u16 *)port;
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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p = (volatile u16 *)PCI_IOMAP(port);
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else
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p = (volatile u16 *)port2adr(port);
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while (count--)
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*p = *buf++;
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}
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void r7780rp_outsl(unsigned long port, const void *src, unsigned long count)
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{
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const u32 *buf = src;
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if (CHECK_AX88796L_PORT(port))
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maybebadio(port);
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) {
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volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);
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while (count--)
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*p = *buf++;
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} else
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maybebadio(port);
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}
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void __iomem *r7780rp_ioport_map(unsigned long port, unsigned int size)
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{
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if (CHECK_AX88796L_PORT(port))
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return (void __iomem *)port88796l(port, size > 1);
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else if (PXSEG(port))
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return (void __iomem *)port;
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else if (CHECK_SH7780_PCIIO(port) || shifted_port(port))
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return (void __iomem *)PCI_IOMAP(port);
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return (void __iomem *)port2adr(port);
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}
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123
arch/sh/boards/renesas/r7780rp/irq.c
Normal file
123
arch/sh/boards/renesas/r7780rp/irq.c
Normal file
@ -0,0 +1,123 @@
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/*
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* linux/arch/sh/boards/renesas/r7780rp/irq.c
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*
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* Copyright (C) 2000 Kazumoto Kojima
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*
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* Renesas Solutions Highlander R7780RP-1 Support.
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*
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* Modified for R7780RP-1 by
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* Atom Create Engineering Co., Ltd. 2002.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/r7780rp/r7780rp.h>
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#ifdef CONFIG_SH_R7780MP
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static int mask_pos[] = {12, 11, 9, 14, 15, 8, 13, 6, 5, 4, 3, 2, 0, 0, 1, 0};
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#else
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static int mask_pos[] = {15, 14, 13, 12, 11, 10, 9, 8, 7, 5, 6, 4, 0, 1, 2, 0};
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#endif
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static void enable_r7780rp_irq(unsigned int irq);
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static void disable_r7780rp_irq(unsigned int irq);
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/* shutdown is same as "disable" */
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#define shutdown_r7780rp_irq disable_r7780rp_irq
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static void ack_r7780rp_irq(unsigned int irq);
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static void end_r7780rp_irq(unsigned int irq);
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static unsigned int startup_r7780rp_irq(unsigned int irq)
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{
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enable_r7780rp_irq(irq);
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return 0; /* never anything pending */
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}
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static void disable_r7780rp_irq(unsigned int irq)
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{
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unsigned long flags;
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unsigned short val;
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unsigned short mask = 0xffff ^ (0x0001 << mask_pos[irq]);
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/* Set the priority in IPR to 0 */
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local_irq_save(flags);
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val = ctrl_inw(IRLCNTR1);
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val &= mask;
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ctrl_outw(val, IRLCNTR1);
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local_irq_restore(flags);
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}
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static void enable_r7780rp_irq(unsigned int irq)
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{
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unsigned long flags;
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unsigned short val;
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unsigned short value = (0x0001 << mask_pos[irq]);
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/* Set priority in IPR back to original value */
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local_irq_save(flags);
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val = ctrl_inw(IRLCNTR1);
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val |= value;
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ctrl_outw(val, IRLCNTR1);
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local_irq_restore(flags);
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}
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static void ack_r7780rp_irq(unsigned int irq)
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{
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disable_r7780rp_irq(irq);
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}
|
||||
|
||||
static void end_r7780rp_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_r7780rp_irq(irq);
|
||||
}
|
||||
|
||||
static struct hw_interrupt_type r7780rp_irq_type = {
|
||||
.typename = "R7780RP-IRQ",
|
||||
.startup = startup_r7780rp_irq,
|
||||
.shutdown = shutdown_r7780rp_irq,
|
||||
.enable = enable_r7780rp_irq,
|
||||
.disable = disable_r7780rp_irq,
|
||||
.ack = ack_r7780rp_irq,
|
||||
.end = end_r7780rp_irq,
|
||||
};
|
||||
|
||||
static void make_r7780rp_irq(unsigned int irq)
|
||||
{
|
||||
disable_irq_nosync(irq);
|
||||
irq_desc[irq].handler = &r7780rp_irq_type;
|
||||
disable_r7780rp_irq(irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize IRQ setting
|
||||
*/
|
||||
void __init init_r7780rp_IRQ(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* IRL0=PCI Slot #A
|
||||
* IRL1=PCI Slot #B
|
||||
* IRL2=PCI Slot #C
|
||||
* IRL3=PCI Slot #D
|
||||
* IRL4=CF Card
|
||||
* IRL5=CF Card Insert
|
||||
* IRL6=M66596
|
||||
* IRL7=SD Card
|
||||
* IRL8=Touch Panel
|
||||
* IRL9=SCI
|
||||
* IRL10=Serial
|
||||
* IRL11=Extention #A
|
||||
* IRL11=Extention #B
|
||||
* IRL12=Debug LAN
|
||||
* IRL13=Push Switch
|
||||
* IRL14=ZiggBee IO
|
||||
*/
|
||||
|
||||
for (i=0; i<15; i++)
|
||||
make_r7780rp_irq(i);
|
||||
}
|
||||
45
arch/sh/boards/renesas/r7780rp/led.c
Normal file
45
arch/sh/boards/renesas/r7780rp/led.c
Normal file
@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (C) Atom Create Engineering Co., Ltd.
|
||||
*
|
||||
* May be copied or modified under the terms of GNU General Public
|
||||
* License. See linux/COPYING for more information.
|
||||
*
|
||||
* This file contains Renesas Solutions HIGHLANDER R7780RP-1 specific LED code.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/sched.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/r7780rp/r7780rp.h>
|
||||
|
||||
/* Cycle the LED's in the clasic Knightriger/Sun pattern */
|
||||
void heartbeat_r7780rp(void)
|
||||
{
|
||||
static unsigned int cnt = 0, period = 0;
|
||||
volatile unsigned short *p = (volatile unsigned short *)PA_OBLED;
|
||||
static unsigned bit = 0, up = 1;
|
||||
unsigned bit_pos[] = {2, 1, 0, 3, 6, 5, 4, 7};
|
||||
|
||||
cnt += 1;
|
||||
if (cnt < period)
|
||||
return;
|
||||
|
||||
cnt = 0;
|
||||
|
||||
/* Go through the points (roughly!):
|
||||
* f(0)=10, f(1)=16, f(2)=20, f(5)=35, f(int)->110
|
||||
*/
|
||||
period = 110 - ((300 << FSHIFT)/((avenrun[0]/5) + (3<<FSHIFT)));
|
||||
|
||||
*p = 1 << bit_pos[bit];
|
||||
if (up)
|
||||
if (bit == 7) {
|
||||
bit--;
|
||||
up = 0;
|
||||
} else
|
||||
bit++;
|
||||
else if (bit == 0)
|
||||
up = 1;
|
||||
else
|
||||
bit--;
|
||||
}
|
||||
164
arch/sh/boards/renesas/r7780rp/setup.c
Normal file
164
arch/sh/boards/renesas/r7780rp/setup.c
Normal file
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* arch/sh/boards/renesas/r7780rp/setup.c
|
||||
*
|
||||
* Copyright (C) 2002 Atom Create Engineering Co., Ltd.
|
||||
* Copyright (C) 2005, 2006 Paul Mundt
|
||||
*
|
||||
* Renesas Solutions Highlander R7780RP-1 Support.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/machvec.h>
|
||||
#include <asm/r7780rp/r7780rp.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
extern void heartbeat_r7780rp(void);
|
||||
extern void init_r7780rp_IRQ(void);
|
||||
|
||||
/*
|
||||
* The Machine Vector
|
||||
*/
|
||||
struct sh_machine_vector mv_r7780rp __initmv = {
|
||||
.mv_nr_irqs = 109,
|
||||
|
||||
.mv_inb = r7780rp_inb,
|
||||
.mv_inw = r7780rp_inw,
|
||||
.mv_inl = r7780rp_inl,
|
||||
.mv_outb = r7780rp_outb,
|
||||
.mv_outw = r7780rp_outw,
|
||||
.mv_outl = r7780rp_outl,
|
||||
|
||||
.mv_inb_p = r7780rp_inb_p,
|
||||
.mv_inw_p = r7780rp_inw,
|
||||
.mv_inl_p = r7780rp_inl,
|
||||
.mv_outb_p = r7780rp_outb_p,
|
||||
.mv_outw_p = r7780rp_outw,
|
||||
.mv_outl_p = r7780rp_outl,
|
||||
|
||||
.mv_insb = r7780rp_insb,
|
||||
.mv_insw = r7780rp_insw,
|
||||
.mv_insl = r7780rp_insl,
|
||||
.mv_outsb = r7780rp_outsb,
|
||||
.mv_outsw = r7780rp_outsw,
|
||||
.mv_outsl = r7780rp_outsl,
|
||||
|
||||
.mv_ioport_map = r7780rp_ioport_map,
|
||||
.mv_init_irq = init_r7780rp_IRQ,
|
||||
#ifdef CONFIG_HEARTBEAT
|
||||
.mv_heartbeat = heartbeat_r7780rp,
|
||||
#endif
|
||||
};
|
||||
ALIAS_MV(r7780rp)
|
||||
|
||||
static struct resource m66596_usb_host_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xa4800000,
|
||||
.end = 0xa4ffffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 6, /* irq number */
|
||||
.end = 6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device m66596_usb_host_device = {
|
||||
.name = "m66596-hcd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = NULL, /* don't use dma */
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(m66596_usb_host_resources),
|
||||
.resource = m66596_usb_host_resources,
|
||||
};
|
||||
|
||||
static struct platform_device *r7780rp_devices[] __initdata = {
|
||||
&m66596_usb_host_device,
|
||||
};
|
||||
|
||||
static int __init r7780rp_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(r7780rp_devices,
|
||||
ARRAY_SIZE(r7780rp_devices));
|
||||
}
|
||||
__initcall(r7780rp_devices_setup);
|
||||
|
||||
/*
|
||||
* Platform specific clocks
|
||||
*/
|
||||
static void ivdr_clk_enable(struct clk *clk)
|
||||
{
|
||||
ctrl_outw(ctrl_inw(PA_IVDRCTL) | (1 << 8), PA_IVDRCTL);
|
||||
}
|
||||
|
||||
static void ivdr_clk_disable(struct clk *clk)
|
||||
{
|
||||
ctrl_outw(ctrl_inw(PA_IVDRCTL) & ~(1 << 8), PA_IVDRCTL);
|
||||
}
|
||||
|
||||
static struct clk_ops ivdr_clk_ops = {
|
||||
.enable = ivdr_clk_enable,
|
||||
.disable = ivdr_clk_disable,
|
||||
};
|
||||
|
||||
static struct clk ivdr_clk = {
|
||||
.name = "ivdr_clk",
|
||||
.ops = &ivdr_clk_ops,
|
||||
};
|
||||
|
||||
static struct clk *r7780rp_clocks[] = {
|
||||
&ivdr_clk,
|
||||
};
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
return "Highlander R7780RP-1";
|
||||
}
|
||||
|
||||
static void r7780rp_power_off(void)
|
||||
{
|
||||
#ifdef CONFIG_SH_R7780MP
|
||||
ctrl_outw(0x0001, PA_POFF);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the board
|
||||
*/
|
||||
void __init platform_setup(void)
|
||||
{
|
||||
u16 ver = ctrl_inw(PA_VERREG);
|
||||
int i;
|
||||
|
||||
printk(KERN_INFO "Renesas Solutions Highlander R7780RP-1 support.\n");
|
||||
|
||||
printk(KERN_INFO "Board version: %d (revision %d), "
|
||||
"FPGA version: %d (revision %d)\n",
|
||||
(ver >> 12) & 0xf, (ver >> 8) & 0xf,
|
||||
(ver >> 4) & 0xf, ver & 0xf);
|
||||
|
||||
/*
|
||||
* Enable the important clocks right away..
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(r7780rp_clocks); i++) {
|
||||
struct clk *clk = r7780rp_clocks[i];
|
||||
|
||||
clk_register(clk);
|
||||
clk_enable(clk);
|
||||
}
|
||||
|
||||
ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */
|
||||
#ifndef CONFIG_SH_R7780MP
|
||||
ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */
|
||||
#endif
|
||||
ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x0100, PA_IVDRCTL); /* Si13112 */
|
||||
|
||||
pm_power_off = r7780rp_power_off;
|
||||
}
|
||||
1099
arch/sh/configs/r7780rp_defconfig
Normal file
1099
arch/sh/configs/r7780rp_defconfig
Normal file
File diff suppressed because it is too large
Load Diff
@ -11,6 +11,8 @@ config SH_DMA
|
||||
config NR_ONCHIP_DMA_CHANNELS
|
||||
depends on SH_DMA
|
||||
int "Number of on-chip DMAC channels"
|
||||
default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
|
||||
default "12" if CPU_SUBTYPE_SH7780
|
||||
default "4"
|
||||
help
|
||||
This allows you to specify the number of channels that the on-chip
|
||||
@ -52,4 +54,3 @@ config DMA_PAGE_OPS_CHANNEL
|
||||
are dual-address capable.
|
||||
|
||||
endmenu
|
||||
|
||||
|
||||
@ -11,14 +11,10 @@
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/dreamcast/dma.h>
|
||||
#include <asm/signal.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/dma.h>
|
||||
#include <asm/io.h>
|
||||
#include "dma-sh.h"
|
||||
|
||||
@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o
|
||||
|
||||
obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o
|
||||
|
||||
obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
|
||||
dma-dreamcast.o
|
||||
@ -14,4 +15,5 @@ obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o
|
||||
obj-$(CONFIG_SH_BIGSUR) += ops-bigsur.o
|
||||
obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o
|
||||
obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o
|
||||
obj-$(CONFIG_SH_R7780RP) += ops-r7780rp.o fixups-r7780rp.o
|
||||
obj-$(CONFIG_SH_TITAN) += ops-titan.o
|
||||
|
||||
39
arch/sh/drivers/pci/fixups-r7780rp.c
Normal file
39
arch/sh/drivers/pci/fixups-r7780rp.c
Normal file
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* arch/sh/drivers/pci/fixups-r7780rp.c
|
||||
*
|
||||
* Highlander R7780RP-1 PCI fixups
|
||||
*
|
||||
* Copyright (C) 2003 Lineo uSolutions, Inc.
|
||||
* Copyright (C) 2004 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include "pci-sh7780.h"
|
||||
#include <asm/io.h>
|
||||
|
||||
int pci_fixup_pcic(void)
|
||||
{
|
||||
outl(0x000043ff, PCI_REG(SH7780_PCIIMR));
|
||||
outl(0x0000380f, PCI_REG(SH7780_PCIAINTM));
|
||||
|
||||
outl(0xfbb00047, PCI_REG(SH7780_PCICMD));
|
||||
outl(0x00000000, PCI_REG(SH7780_PCIIBAR));
|
||||
|
||||
outl(0x00011912, PCI_REG(SH7780_PCISVID));
|
||||
outl(0x08000000, PCI_REG(SH7780_PCICSCR0));
|
||||
outl(0x0000001b, PCI_REG(SH7780_PCICSAR0));
|
||||
outl(0xfd000000, PCI_REG(SH7780_PCICSCR1));
|
||||
outl(0x0000000f, PCI_REG(SH7780_PCICSAR1));
|
||||
|
||||
outl(0xfd000000, PCI_REG(SH7780_PCIMBR0));
|
||||
outl(0x00fc0000, PCI_REG(SH7780_PCIMBMR0));
|
||||
|
||||
/* Set IOBR for windows containing area specified in pci.h */
|
||||
outl((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1)), PCI_REG(SH7780_PCIIOBR));
|
||||
outl(((SH7780_PCI_IO_SIZE-1) & (7<<18)), PCI_REG(SH7780_PCIIOBMR));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
77
arch/sh/drivers/pci/ops-r7780rp.c
Normal file
77
arch/sh/drivers/pci/ops-r7780rp.c
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Author: Ian DaSilva (idasilva@mvista.com)
|
||||
*
|
||||
* Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
|
||||
*
|
||||
* May be copied or modified under the terms of the GNU General Public
|
||||
* License. See linux/COPYING for more information.
|
||||
*
|
||||
* PCI initialization for the Renesas SH7780 Highlander R7780RP-1 board
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include "pci-sh7780.h"
|
||||
#include <asm/r7780rp/r7780rp.h>
|
||||
|
||||
int __init pcibios_map_platform_irq(u8 slot, u8 pin)
|
||||
{
|
||||
switch (slot) {
|
||||
case 0: return IRQ_PCISLOT1; /* PCI Interrupt #1 */
|
||||
case 1: return IRQ_PCISLOT2; /* PCI Interrupt #2 */
|
||||
case 2: return IRQ_PCISLOT3; /* PCI Interrupt #3 */
|
||||
case 3: return IRQ_PCISLOT4; /* PCI Interrupt E4 */
|
||||
default:
|
||||
printk("PCI: Bad IRQ mapping request for slot %d, func %d\n", slot, pin-1);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static struct resource sh7780_io_resource = {
|
||||
.name = "SH7780_IO",
|
||||
.start = 0x2000,
|
||||
.end = 0x2000 + SH7780_PCI_IO_SIZE - 1,
|
||||
.flags = IORESOURCE_IO
|
||||
};
|
||||
|
||||
static struct resource sh7780_mem_resource = {
|
||||
.name = "SH7780_mem",
|
||||
.start = SH7780_PCI_MEMORY_BASE,
|
||||
.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM
|
||||
};
|
||||
|
||||
extern struct pci_ops sh7780_pci_ops;
|
||||
|
||||
struct pci_channel board_pci_channels[] = {
|
||||
{ &sh7780_pci_ops, &sh7780_io_resource, &sh7780_mem_resource, 0, 0xff },
|
||||
{ NULL, NULL, NULL, 0, 0 },
|
||||
};
|
||||
EXPORT_SYMBOL(board_pci_channels);
|
||||
|
||||
static struct sh7780_pci_address_map sh7780_pci_map = {
|
||||
.window0 = {
|
||||
.base = SH7780_CS2_BASE_ADDR,
|
||||
.size = 0x04000000,
|
||||
},
|
||||
|
||||
.window1 = {
|
||||
.base = SH7780_CS3_BASE_ADDR,
|
||||
.size = 0x04000000,
|
||||
},
|
||||
|
||||
.flags = SH7780_PCIC_NO_RESET,
|
||||
};
|
||||
|
||||
int __init pcibios_init_platform(void)
|
||||
{
|
||||
return sh7780_pcic_init(&sh7780_pci_map);
|
||||
}
|
||||
|
||||
@ -45,11 +45,11 @@
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#undef DEBUG
|
||||
#ifdef DEBUG
|
||||
#define DEBUG
|
||||
#ifdef DEBUG
|
||||
#define DBG(x...) printk(x)
|
||||
#else
|
||||
#define DBG(x...)
|
||||
#define DBG(x...)
|
||||
#endif
|
||||
|
||||
/*
|
||||
@ -102,7 +102,7 @@ static u32 pciauto_upper_iospc;
|
||||
static u32 pciauto_lower_memspc;
|
||||
static u32 pciauto_upper_memspc;
|
||||
|
||||
static void __init
|
||||
static void __init
|
||||
pciauto_setup_bars(struct pci_channel *hose,
|
||||
int top_bus,
|
||||
int current_bus,
|
||||
@ -116,7 +116,6 @@ pciauto_setup_bars(struct pci_channel *hose,
|
||||
int found_mem64 = 0;
|
||||
|
||||
for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
|
||||
#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
|
||||
u32 bar_addr;
|
||||
|
||||
/* Read the old BAR value */
|
||||
@ -125,7 +124,6 @@ pciauto_setup_bars(struct pci_channel *hose,
|
||||
pci_devfn,
|
||||
bar,
|
||||
&bar_addr);
|
||||
#endif
|
||||
|
||||
/* Tickle the BAR and get the response */
|
||||
early_write_config_dword(hose, top_bus,
|
||||
@ -140,8 +138,7 @@ pciauto_setup_bars(struct pci_channel *hose,
|
||||
bar,
|
||||
&bar_response);
|
||||
|
||||
#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
|
||||
/*
|
||||
/*
|
||||
* Write the old BAR value back out, only update the BAR
|
||||
* if we implicitly want resources to be updated, which
|
||||
* is done by the generic code further down. -- PFM.
|
||||
@ -151,7 +148,6 @@ pciauto_setup_bars(struct pci_channel *hose,
|
||||
pci_devfn,
|
||||
bar,
|
||||
bar_addr);
|
||||
#endif
|
||||
|
||||
/* If BAR is not implemented go to the next BAR */
|
||||
if (!bar_response)
|
||||
@ -177,7 +173,7 @@ pciauto_setup_bars(struct pci_channel *hose,
|
||||
PCI_BASE_ADDRESS_MEM_TYPE_64)
|
||||
found_mem64 = 1;
|
||||
|
||||
addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
|
||||
addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
|
||||
upper_limit = &pciauto_upper_memspc;
|
||||
lower_limit = &pciauto_lower_memspc;
|
||||
DBG(" Mem");
|
||||
@ -193,22 +189,22 @@ pciauto_setup_bars(struct pci_channel *hose,
|
||||
if ((bar_value + bar_size) > *upper_limit) {
|
||||
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
|
||||
if (io_resource_inuse->child) {
|
||||
io_resource_inuse =
|
||||
io_resource_inuse =
|
||||
io_resource_inuse->child;
|
||||
pciauto_lower_iospc =
|
||||
pciauto_lower_iospc =
|
||||
io_resource_inuse->start;
|
||||
pciauto_upper_iospc =
|
||||
pciauto_upper_iospc =
|
||||
io_resource_inuse->end + 1;
|
||||
goto retry;
|
||||
}
|
||||
|
||||
} else {
|
||||
if (mem_resource_inuse->child) {
|
||||
mem_resource_inuse =
|
||||
mem_resource_inuse =
|
||||
mem_resource_inuse->child;
|
||||
pciauto_lower_memspc =
|
||||
pciauto_lower_memspc =
|
||||
mem_resource_inuse->start;
|
||||
pciauto_upper_memspc =
|
||||
pciauto_upper_memspc =
|
||||
mem_resource_inuse->end + 1;
|
||||
goto retry;
|
||||
}
|
||||
@ -230,7 +226,7 @@ pciauto_setup_bars(struct pci_channel *hose,
|
||||
* If we are a 64-bit decoder then increment to the
|
||||
* upper 32 bits of the bar and force it to locate
|
||||
* in the lower 4GB of memory.
|
||||
*/
|
||||
*/
|
||||
if (found_mem64) {
|
||||
bar += 4;
|
||||
early_write_config_dword(hose, top_bus,
|
||||
@ -362,7 +358,7 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
|
||||
#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D) && !defined(CONFIG_SH_R7780RP)
|
||||
/*
|
||||
* [jsun] we always bump up baselines a little, so that if there
|
||||
* nothing behind P2P bridge, we don't wind up overlapping IO/MEM
|
||||
@ -396,7 +392,7 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
|
||||
* configured by this routine to happily live behind a
|
||||
* P2P bridge in a system.
|
||||
*/
|
||||
#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
|
||||
#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP)
|
||||
pciauto_lower_memspc += 0x00400000;
|
||||
pciauto_lower_iospc += 0x00004000;
|
||||
#endif
|
||||
@ -433,12 +429,12 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
|
||||
int devfn_stop = 0xff;
|
||||
|
||||
sub_bus = current_bus;
|
||||
|
||||
|
||||
if (hose->first_devfn)
|
||||
devfn_start = hose->first_devfn;
|
||||
if (hose->last_devfn)
|
||||
devfn_stop = hose->last_devfn;
|
||||
|
||||
|
||||
for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
|
||||
|
||||
if (PCI_FUNC(pci_devfn) && !found_multi)
|
||||
@ -471,7 +467,7 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
|
||||
if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
|
||||
DBG(" Bridge: primary=%.2x, secondary=%.2x\n",
|
||||
current_bus, sub_bus + 1);
|
||||
#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
|
||||
#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP)
|
||||
pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1);
|
||||
#endif
|
||||
pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
|
||||
@ -490,10 +486,10 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
|
||||
DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
|
||||
/* Place CardBus Socket/ExCA registers */
|
||||
pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
|
||||
|
||||
|
||||
pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
|
||||
current_bus, pci_devfn, sub_bus);
|
||||
|
||||
|
||||
DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
|
||||
sub_bus + 1,
|
||||
pciauto_lower_iospc, pciauto_lower_memspc);
|
||||
|
||||
@ -223,7 +223,7 @@ static int __init __area_sdram_check(unsigned int area)
|
||||
|
||||
word = inl(SH7751_BCR1);
|
||||
/* check BCR for SDRAM in area */
|
||||
if(((word >> area) & 1) == 0) {
|
||||
if (((word >> area) & 1) == 0) {
|
||||
printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
|
||||
area, word);
|
||||
return 0;
|
||||
@ -232,7 +232,7 @@ static int __init __area_sdram_check(unsigned int area)
|
||||
|
||||
word = (u16)inw(SH7751_BCR2);
|
||||
/* check BCR2 for 32bit SDRAM interface*/
|
||||
if(((word >> (area << 1)) & 0x3) != 0x3) {
|
||||
if (((word >> (area << 1)) & 0x3) != 0x3) {
|
||||
printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
|
||||
area, word);
|
||||
return 0;
|
||||
|
||||
341
arch/sh/drivers/pci/pci-sh7780.c
Normal file
341
arch/sh/drivers/pci/pci-sh7780.c
Normal file
@ -0,0 +1,341 @@
|
||||
/*
|
||||
* Low-Level PCI Support for the SH7780
|
||||
*
|
||||
* Dustin McIntire (dustin@sensoria.com)
|
||||
* Derived from arch/i386/kernel/pci-*.c which bore the message:
|
||||
* (c) 1999--2000 Martin Mares <mj@ucw.cz>
|
||||
*
|
||||
* Ported to the new API by Paul Mundt <lethal@linux-sh.org>
|
||||
* With cleanup by Paul van Gool <pvangool@mimotech.com>
|
||||
*
|
||||
* May be copied or modified under the terms of the GNU General Public
|
||||
* License. See linux/COPYING for more information.
|
||||
*
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <asm/machvec.h>
|
||||
#include <asm/io.h>
|
||||
#include "pci-sh7780.h"
|
||||
|
||||
static unsigned int pci_probe = PCI_PROBE_CONF1;
|
||||
extern int pci_fixup_pcic(void);
|
||||
|
||||
/*
|
||||
* Direct access to PCI hardware...
|
||||
*/
|
||||
|
||||
#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
|
||||
|
||||
/*
|
||||
* Functions for accessing PCI configuration space with type 1 accesses
|
||||
*/
|
||||
static int sh7780_pci_read(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 *val)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 data;
|
||||
|
||||
/*
|
||||
* PCIPDR may only be accessed as 32 bit words,
|
||||
* so we must do byte alignment by hand
|
||||
*/
|
||||
local_irq_save(flags);
|
||||
outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR));
|
||||
data = inl(PCI_REG(SH7780_PCIPDR));
|
||||
local_irq_restore(flags);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
*val = (data >> ((where & 3) << 3)) & 0xff;
|
||||
break;
|
||||
case 2:
|
||||
*val = (data >> ((where & 2) << 3)) & 0xffff;
|
||||
break;
|
||||
case 4:
|
||||
*val = data;
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_FUNC_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Since SH7780 only does 32bit access we'll have to do a read,
|
||||
* mask,write operation.
|
||||
* We'll allow an odd byte offset, though it should be illegal.
|
||||
*/
|
||||
static int sh7780_pci_write(struct pci_bus *bus, unsigned int devfn,
|
||||
int where, int size, u32 val)
|
||||
{
|
||||
unsigned long flags;
|
||||
int shift;
|
||||
u32 data;
|
||||
|
||||
local_irq_save(flags);
|
||||
outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR));
|
||||
data = inl(PCI_REG(SH7780_PCIPDR));
|
||||
local_irq_restore(flags);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
shift = (where & 3) << 3;
|
||||
data &= ~(0xff << shift);
|
||||
data |= ((val & 0xff) << shift);
|
||||
break;
|
||||
case 2:
|
||||
shift = (where & 2) << 3;
|
||||
data &= ~(0xffff << shift);
|
||||
data |= ((val & 0xffff) << shift);
|
||||
break;
|
||||
case 4:
|
||||
data = val;
|
||||
break;
|
||||
default:
|
||||
return PCIBIOS_FUNC_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
outl(data, PCI_REG(SH7780_PCIPDR));
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
#undef CONFIG_CMD
|
||||
|
||||
struct pci_ops sh7780_pci_ops = {
|
||||
.read = sh7780_pci_read,
|
||||
.write = sh7780_pci_write,
|
||||
};
|
||||
|
||||
static int __init pci_check_direct(void)
|
||||
{
|
||||
unsigned int tmp, id;
|
||||
|
||||
outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
|
||||
|
||||
/* check for SH7780/SH7780R hardware */
|
||||
id = inl(PCI_REG(SH7780_PCIVID));
|
||||
if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) &&
|
||||
(id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) {
|
||||
printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if configuration works.
|
||||
*/
|
||||
if (pci_probe & PCI_PROBE_CONF1) {
|
||||
tmp = inl(PCI_REG(SH7780_PCIPAR));
|
||||
outl(0x80000000, PCI_REG(SH7780_PCIPAR));
|
||||
if (inl(PCI_REG(SH7780_PCIPAR)) == 0x80000000) {
|
||||
outl(tmp, PCI_REG(SH7780_PCIPAR));
|
||||
printk(KERN_INFO "PCI: Using configuration type 1\n");
|
||||
request_region(PCI_REG(SH7780_PCIPAR), 8, "PCI conf1");
|
||||
return 0;
|
||||
}
|
||||
outl(tmp, PCI_REG(SH7780_PCIPAR));
|
||||
}
|
||||
|
||||
pr_debug("PCI: pci_check_direct failed\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/***************************************************************************************/
|
||||
|
||||
/*
|
||||
* Handle bus scanning and fixups ....
|
||||
*/
|
||||
|
||||
static void __init pci_fixup_ide_bases(struct pci_dev *d)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* PCI IDE controllers use non-standard I/O port decoding, respect it.
|
||||
*/
|
||||
if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
|
||||
return;
|
||||
pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d));
|
||||
for(i=0; i<4; i++) {
|
||||
struct resource *r = &d->resource[i];
|
||||
if ((r->start & ~0x80) == 0x374) {
|
||||
r->start |= 2;
|
||||
r->end = r->start;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
|
||||
|
||||
/*
|
||||
* Called after each bus is probed, but before its children
|
||||
* are examined.
|
||||
*/
|
||||
|
||||
void __init pcibios_fixup_bus(struct pci_bus *b)
|
||||
{
|
||||
pci_read_bridge_bases(b);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialization. Try all known PCI access methods. Note that we support
|
||||
* using both PCI BIOS and direct access: in such cases, we use I/O ports
|
||||
* to access config space.
|
||||
*
|
||||
* Note that the platform specific initialization (BSC registers, and memory
|
||||
* space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it
|
||||
* exists and via the platform defined function pcibios_init_platform().
|
||||
* See pci_bigsur.c for implementation;
|
||||
*
|
||||
* The BIOS version of the pci functions is not yet implemented but it is left
|
||||
* in for completeness. Currently an error will be genereated at compile time.
|
||||
*/
|
||||
|
||||
static int __init sh7780_pci_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
pr_debug("PCI: Starting intialization.\n");
|
||||
|
||||
/* Setup the INTC */
|
||||
ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */
|
||||
ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */
|
||||
ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */
|
||||
ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */
|
||||
ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */
|
||||
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */
|
||||
|
||||
if ((ret = pci_check_direct()) != 0)
|
||||
return ret;
|
||||
|
||||
return pcibios_init_platform();
|
||||
}
|
||||
|
||||
core_initcall(sh7780_pci_init);
|
||||
|
||||
int __init sh7780_pcic_init(struct sh7780_pci_address_map *map)
|
||||
{
|
||||
u32 word;
|
||||
|
||||
/*
|
||||
* This code is unused for some boards as it is done in the
|
||||
* bootloader and doing it here means the MAC addresses loaded
|
||||
* by the bootloader get lost.
|
||||
*/
|
||||
if (!(map->flags & SH7780_PCIC_NO_RESET)) {
|
||||
/* toggle PCI reset pin */
|
||||
word = SH7780_PCICR_PREFIX | SH7780_PCICR_PRST;
|
||||
outl(word,PCI_REG(SH7780_PCICR));
|
||||
/* Wait for a long time... not 1 sec. but long enough */
|
||||
mdelay(100);
|
||||
word = SH7780_PCICR_PREFIX;
|
||||
outl(word,PCI_REG(SH7780_PCICR));
|
||||
}
|
||||
|
||||
/* set the command/status bits to:
|
||||
* Wait Cycle Control + Parity Enable + Bus Master +
|
||||
* Mem space enable
|
||||
*/
|
||||
outl(0x00000046, PCI_REG(SH7780_PCICMD));
|
||||
|
||||
/* define this host as the host bridge */
|
||||
word = SH7780_PCI_HOST_BRIDGE << 24;
|
||||
outl(word, PCI_REG(SH7780_PCIRID));
|
||||
|
||||
/* Set IO and Mem windows to local address
|
||||
* Make PCI and local address the same for easy 1 to 1 mapping
|
||||
* Window0 = map->window0.size @ non-cached area base = SDRAM
|
||||
* Window1 = map->window1.size @ cached area base = SDRAM
|
||||
*/
|
||||
word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
|
||||
outl(0x07f00001, PCI_REG(SH7780_PCILSR0));
|
||||
word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
|
||||
outl(0x00000001, PCI_REG(SH7780_PCILSR1));
|
||||
/* Set the values on window 0 PCI config registers */
|
||||
word = P2SEGADDR(map->window0.base);
|
||||
outl(0xa8000000, PCI_REG(SH7780_PCILAR0));
|
||||
outl(0x08000000, PCI_REG(SH7780_PCIMBAR0));
|
||||
/* Set the values on window 1 PCI config registers */
|
||||
word = P2SEGADDR(map->window1.base);
|
||||
outl(0x00000000, PCI_REG(SH7780_PCILAR1));
|
||||
outl(0x00000000, PCI_REG(SH7780_PCIMBAR1));
|
||||
|
||||
/* Map IO space into PCI IO window
|
||||
* The IO window is 64K-PCIBIOS_MIN_IO in size
|
||||
* IO addresses will be translated to the
|
||||
* PCI IO window base address
|
||||
*/
|
||||
PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
|
||||
(64*1024), SH7780_PCI_IO_BASE+PCIBIOS_MIN_IO);
|
||||
|
||||
/* NOTE: I'm ignoring the PCI error IRQs for now..
|
||||
* TODO: add support for the internal error interrupts and
|
||||
* DMA interrupts...
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SH_R7780RP
|
||||
pci_fixup_pcic();
|
||||
#endif
|
||||
|
||||
/* SH7780 init done, set central function init complete */
|
||||
/* use round robin mode to stop a device starving/overruning */
|
||||
word = SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | /* SH7780_PCICR_ARBM |*/ SH7780_PCICR_FTO;
|
||||
outl(word, PCI_REG(SH7780_PCICR));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
char * __init pcibios_setup(char *str)
|
||||
{
|
||||
if (!strcmp(str, "off")) {
|
||||
pci_probe = 0;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
/*
|
||||
* IRQ functions
|
||||
*/
|
||||
static u8 __init sh7780_no_swizzle(struct pci_dev *dev, u8 *pin)
|
||||
{
|
||||
/* no swizzling */
|
||||
return PCI_SLOT(dev->devfn);
|
||||
}
|
||||
|
||||
static int sh7780_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
int irq = -1;
|
||||
|
||||
/* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
|
||||
irq = pcibios_map_platform_irq(slot,pin);
|
||||
if( irq < 0 ) {
|
||||
pr_debug("PCI: Error mapping IRQ on device %s\n", pci_name(dev));
|
||||
return irq;
|
||||
}
|
||||
|
||||
pr_debug("Setting IRQ for slot %s to %d\n", pci_name(dev), irq);
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
void __init pcibios_fixup_irqs(void)
|
||||
{
|
||||
pci_fixup_irqs(sh7780_no_swizzle, sh7780_pci_lookup_irq);
|
||||
}
|
||||
|
||||
168
arch/sh/drivers/pci/pci-sh7780.h
Normal file
168
arch/sh/drivers/pci/pci-sh7780.h
Normal file
@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Low-Level PCI Support for SH7780 targets
|
||||
*
|
||||
* Dustin McIntire (dustin@sensoria.com) (c) 2001
|
||||
* Paul Mundt (lethal@linux-sh.org) (c) 2003
|
||||
*
|
||||
* May be copied or modified under the terms of the GNU General Public
|
||||
* License. See linux/COPYING for more information.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _PCI_SH7780_H_
|
||||
#define _PCI_SH7780_H_
|
||||
|
||||
#include <linux/pci.h>
|
||||
|
||||
/* set debug level 4=verbose...1=terse */
|
||||
//#define DEBUG_PCI 3
|
||||
#undef DEBUG_PCI
|
||||
|
||||
#ifdef DEBUG_PCI
|
||||
#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
|
||||
#else
|
||||
#define PCIDBG(n, x...)
|
||||
#endif
|
||||
|
||||
/* startup values */
|
||||
#define PCI_PROBE_BIOS 1
|
||||
#define PCI_PROBE_CONF1 2
|
||||
#define PCI_PROBE_CONF2 4
|
||||
#define PCI_NO_SORT 0x100
|
||||
#define PCI_BIOS_SORT 0x200
|
||||
#define PCI_NO_CHECKS 0x400
|
||||
#define PCI_ASSIGN_ROMS 0x1000
|
||||
#define PCI_BIOS_IRQ_SCAN 0x2000
|
||||
|
||||
/* Platform Specific Values */
|
||||
#define SH7780_VENDOR_ID 0x1912
|
||||
#define SH7780_DEVICE_ID 0x0002
|
||||
#define SH7781_DEVICE_ID 0x0001
|
||||
|
||||
/* SH7780 Control Registers */
|
||||
#define SH7780_PCI_VCR0 0xFE000000
|
||||
#define SH7780_PCI_VCR1 0xFE000004
|
||||
#define SH7780_PCI_VCR2 0xFE000008
|
||||
|
||||
/* SH7780 Specific Values */
|
||||
#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
|
||||
#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
|
||||
#define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
|
||||
#define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
|
||||
#if 1
|
||||
#define SH7780_PCI_IO_BASE 0xFE400000 /* IO space base address */
|
||||
#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
|
||||
#else
|
||||
#define SH7780_PCI_IO_BASE 0xFE200000 /* IO space base address */
|
||||
#define SH7780_PCI_IO_SIZE 0x00200000 /* Size of IO window */
|
||||
#endif
|
||||
|
||||
#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
|
||||
#define PCI_REG(n) (SH7780_PCIREG_BASE+n)
|
||||
|
||||
/* SH7780 PCI Config Registers */
|
||||
#define SH7780_PCIVID 0x000 /* Vendor ID */
|
||||
#define SH7780_PCIDID 0x002 /* Device ID */
|
||||
#define SH7780_PCICMD 0x004 /* Command */
|
||||
#define SH7780_PCISTATUS 0x006 /* Status */
|
||||
#define SH7780_PCIRID 0x008 /* Revision ID */
|
||||
#define SH7780_PCIPIF 0x009 /* Program Interface */
|
||||
#define SH7780_PCISUB 0x00a /* Sub class code */
|
||||
#define SH7780_PCIBCC 0x00b /* Base class code */
|
||||
#define SH7780_PCICLS 0x00c /* Cache line size */
|
||||
#define SH7780_PCILTM 0x00d /* latency timer */
|
||||
#define SH7780_PCIHDR 0x00e /* Header type */
|
||||
#define SH7780_PCIBIST 0x00f /* BIST */
|
||||
#define SH7780_PCIIBAR 0x010 /* IO Base address */
|
||||
#define SH7780_PCIMBAR0 0x014 /* Memory base address0 */
|
||||
#define SH7780_PCIMBAR1 0x018 /* Memory base address1 */
|
||||
#define SH7780_PCISVID 0x02c /* Sub system vendor ID */
|
||||
#define SH7780_PCISID 0x02e /* Sub system ID */
|
||||
#define SH7780_PCICP 0x034
|
||||
#define SH7780_PCIINTLINE 0x03c /* Interrupt line */
|
||||
#define SH7780_PCIINTPIN 0x03d /* Interrupt pin */
|
||||
#define SH7780_PCIMINGNT 0x03e /* Minumum grand */
|
||||
#define SH7780_PCIMAXLAT 0x03f /* Maxmum latency */
|
||||
#define SH7780_PCICID 0x040
|
||||
#define SH7780_PCINIP 0x041
|
||||
#define SH7780_PCIPMC 0x042
|
||||
#define SH7780_PCIPMCSR 0x044
|
||||
#define SH7780_PCIPMCSR_BSE 0x046
|
||||
#define SH7780_PCICDD 0x047
|
||||
|
||||
/* SH7780 PCI Local Registers */
|
||||
#define SH7780_PCICR 0x100 /* PCI Control Register */
|
||||
#define SH7780_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
|
||||
#define SH7780_PCICR_PFCS 0x00000800 /* TRDY/IRDY Enable */
|
||||
#define SH7780_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
|
||||
#define SH7780_PCICR_PFE 0x00000200 /* Target Read Single */
|
||||
#define SH7780_PCICR_TBS 0x00000100 /* Target Byte Swap */
|
||||
#define SH7780_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
|
||||
#define SH7780_PCICR_IOCS 0x00000004 /* INTA output assert */
|
||||
#define SH7780_PCICR_PRST 0x00000002 /* PCI Reset Assert */
|
||||
#define SH7780_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
|
||||
#define SH7780_PCILSR0 0x104 /* PCI Local Space Register0 */
|
||||
#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
|
||||
#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
|
||||
#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
|
||||
#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
|
||||
#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
|
||||
#define SH7780_PCIAIR 0x11C /* Error Address Register */
|
||||
#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
|
||||
#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
|
||||
#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
|
||||
#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
|
||||
#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
|
||||
#define SH7780_PCIPINT 0x1CC /* Power Management Int. Register */
|
||||
#define SH7780_PCIPINTM 0x1D0 /* Power Management Mask Register */
|
||||
#define SH7780_PCIMBR0 0x1E0 /* Memory Bank0 Register */
|
||||
#define SH7780_PCIMBMR0 0x1E4 /* Memory Bank0 Mask Register */
|
||||
#define SH7780_PCIMBR1 0x1E8 /* Memory Bank1 Register */
|
||||
#define SH7780_PCIMBMR1 0x1EC /* Memory Bank1 Mask Register */
|
||||
#define SH7780_PCIMBR2 0x1F0 /* Memory Bank2 Register */
|
||||
#define SH7780_PCIMBMR2 0x1F4 /* Memory Bank2 Mask Register */
|
||||
#define SH7780_PCIIOBR 0x1F8 /* Bank Register */
|
||||
#define SH7780_PCIIOBMR 0x1FC /* Bank Mask Register */
|
||||
#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */
|
||||
#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */
|
||||
#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
|
||||
#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
|
||||
#define SH7780_PCIPDR 0x220 /* Port IO Data Register */
|
||||
|
||||
/* General Memory Config Addresses */
|
||||
#define SH7780_CS0_BASE_ADDR 0x0
|
||||
#define SH7780_MEM_REGION_SIZE 0x04000000
|
||||
#define SH7780_CS1_BASE_ADDR (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
|
||||
#define SH7780_CS2_BASE_ADDR (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
|
||||
#define SH7780_CS3_BASE_ADDR (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
|
||||
#define SH7780_CS4_BASE_ADDR (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
|
||||
#define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
|
||||
#define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
|
||||
|
||||
/* General PCI values */
|
||||
#define SH7780_PCI_HOST_BRIDGE 0x6
|
||||
|
||||
/* Flags */
|
||||
#define SH7780_PCIC_NO_RESET 0x0001
|
||||
|
||||
/* External functions defined per platform i.e. Big Sur, SE... (these could be routed
|
||||
* through the machine vectors... */
|
||||
extern int pcibios_init_platform(void);
|
||||
extern int pcibios_map_platform_irq(u8 slot, u8 pin);
|
||||
|
||||
struct sh7780_pci_address_space {
|
||||
unsigned long base;
|
||||
unsigned long size;
|
||||
};
|
||||
|
||||
struct sh7780_pci_address_map {
|
||||
struct sh7780_pci_address_space window0;
|
||||
struct sh7780_pci_address_space window1;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
/* arch/sh/drivers/pci/pci-sh7780.c */
|
||||
extern int sh7780_pcic_init(struct sh7780_pci_address_map *map);
|
||||
|
||||
#endif /* _PCI_SH7780_H_ */
|
||||
|
||||
@ -241,9 +241,9 @@ static struct intc2_init {
|
||||
/* 110-111 reserved/unused */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
{ TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
|
||||
#ifdef CONFIG_SH_RTC
|
||||
{ RTC_IRQ, 4, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
|
||||
#endif
|
||||
{ 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
|
||||
{ 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
|
||||
{ 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
|
||||
{ SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
|
||||
{ SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
|
||||
{ SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
|
||||
|
||||
@ -26,4 +26,6 @@ EDOSK7705 SH_EDOSK7705
|
||||
SH4202_MICRODEV SH_SH4202_MICRODEV
|
||||
SH03 SH_SH03
|
||||
LANDISK SH_LANDISK
|
||||
R7780RP SH_R7780RP
|
||||
R7780MP SH_R7780MP
|
||||
TITAN SH_TITAN
|
||||
|
||||
@ -22,5 +22,8 @@
|
||||
#define P4SEG_TLB_DATA 0xf7000000
|
||||
#define P4SEG_REG_BASE 0xff000000
|
||||
|
||||
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
|
||||
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
|
||||
|
||||
#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
|
||||
|
||||
|
||||
39
include/asm-sh/cpu-sh4/dma-sh7780.h
Normal file
39
include/asm-sh/cpu-sh4/dma-sh7780.h
Normal file
@ -0,0 +1,39 @@
|
||||
#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
|
||||
#define __ASM_SH_CPU_SH4_DMA_SH7780_H
|
||||
|
||||
#define REQ_HE 0x000000C0
|
||||
#define REQ_H 0x00000080
|
||||
#define REQ_LE 0x00000040
|
||||
#define TM_BURST 0x0000020
|
||||
#define TS_8 0x00000000
|
||||
#define TS_16 0x00000008
|
||||
#define TS_32 0x00000010
|
||||
#define TS_16BLK 0x00000018
|
||||
#define TS_32BLK 0x00100000
|
||||
|
||||
/*
|
||||
* The SuperH DMAC supports a number of transmit sizes, we list them here,
|
||||
* with their respective values as they appear in the CHCR registers.
|
||||
*
|
||||
* Defaults to a 64-bit transfer size.
|
||||
*/
|
||||
enum {
|
||||
XMIT_SZ_8BIT,
|
||||
XMIT_SZ_16BIT,
|
||||
XMIT_SZ_32BIT,
|
||||
XMIT_SZ_128BIT,
|
||||
XMIT_SZ_256BIT,
|
||||
};
|
||||
|
||||
/*
|
||||
* The DMA count is defined as the number of bytes to transfer.
|
||||
*/
|
||||
static unsigned int __attribute__ ((used)) ts_shift[] = {
|
||||
[XMIT_SZ_8BIT] = 0,
|
||||
[XMIT_SZ_16BIT] = 1,
|
||||
[XMIT_SZ_32BIT] = 2,
|
||||
[XMIT_SZ_128BIT] = 4,
|
||||
[XMIT_SZ_256BIT] = 5,
|
||||
};
|
||||
|
||||
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
|
||||
@ -1,11 +1,17 @@
|
||||
#ifndef __ASM_CPU_SH4_DMA_H
|
||||
#define __ASM_CPU_SH4_DMA_H
|
||||
|
||||
#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
|
||||
|
||||
#ifdef CONFIG_CPU_SH4A
|
||||
#define SH_DMAC_BASE 0xfc808020
|
||||
|
||||
#define CHCR_TS_MASK 0x18
|
||||
#define CHCR_TS_SHIFT 3
|
||||
|
||||
#include <asm/cpu/dma-sh7780.h>
|
||||
#else
|
||||
#define SH_DMAC_BASE 0xffa00000
|
||||
#endif
|
||||
|
||||
/* Definitions for the SuperH DMAC */
|
||||
#define TM_BURST 0x0000080
|
||||
@ -19,8 +25,6 @@
|
||||
|
||||
#define DMAOR_COD 0x00000008
|
||||
|
||||
#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
|
||||
|
||||
/*
|
||||
* The SuperH DMAC supports a number of transmit sizes, we list them here,
|
||||
* with their respective values as they appear in the CHCR registers.
|
||||
@ -45,5 +49,6 @@ static unsigned int ts_shift[] __attribute__ ((used)) = {
|
||||
[XMIT_SZ_32BIT] = 2,
|
||||
[XMIT_SZ_256BIT] = 5,
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CPU_SH4_DMA_H */
|
||||
|
||||
@ -19,8 +19,6 @@
|
||||
#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
|
||||
#define PA_VERREG 0xa4000014 /* FPGA Version Register */
|
||||
|
||||
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
|
||||
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
|
||||
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
|
||||
|
||||
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
|
||||
|
||||
@ -145,11 +145,6 @@
|
||||
#define TMU_CH5_IPR_POS 1
|
||||
#define TMU_CH5_PRIORITY 2
|
||||
|
||||
#define RTC_IRQ 22
|
||||
#define RTC_IPR_ADDR INTC_INT2PRI1
|
||||
#define RTC_IPR_POS 0
|
||||
#define RTC_PRIORITY TIMER_PRIORITY
|
||||
|
||||
/* SCIF0 */
|
||||
#define SCIF0_ERI_IRQ 40
|
||||
#define SCIF0_RXI_IRQ 41
|
||||
|
||||
@ -577,7 +577,7 @@ extern int ipr_irq_demux(int irq);
|
||||
#define NR_INTC2_IRQS 64
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#define INTC2_BASE 0xffd40000
|
||||
#define INTC2_FIRST_IRQ 22
|
||||
#define INTC2_FIRST_IRQ 21
|
||||
#define INTC2_INTMSK_OFFSET (0x38)
|
||||
#define INTC2_INTMSKCLR_OFFSET (0x3c)
|
||||
#define NR_INTC2_IRQS 60
|
||||
|
||||
@ -22,8 +22,6 @@
|
||||
/* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */
|
||||
#define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
|
||||
|
||||
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
|
||||
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
|
||||
#define PA_LCD_CLRDSP 0x00 /* LCD Clear Display Offset */
|
||||
#define PA_LCD_RTNHOME 0x00 /* LCD Return Home Offset */
|
||||
#define PA_LCD_ENTMODE 0x00 /* LCD Entry Mode Offset */
|
||||
|
||||
8
include/asm-sh/r7780rp/ide.h
Normal file
8
include/asm-sh/r7780rp/ide.h
Normal file
@ -0,0 +1,8 @@
|
||||
#ifndef __ASM_SH_R7780RP_IDE_H
|
||||
#define __ASM_SH_R7780RP_IDE_H
|
||||
|
||||
/* Nothing to see here.. */
|
||||
#include <asm/mach/r7780rp.h>
|
||||
|
||||
#endif /* __ASM_SH_R7780RP_IDE_H */
|
||||
|
||||
177
include/asm-sh/r7780rp/r7780rp.h
Normal file
177
include/asm-sh/r7780rp/r7780rp.h
Normal file
@ -0,0 +1,177 @@
|
||||
#ifndef __ASM_SH_RENESAS_R7780RP_H
|
||||
#define __ASM_SH_RENESAS_R7780RP_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/r7780rp.h
|
||||
*
|
||||
* Copyright (C) 2000 Atom Create Engineering Co., Ltd.
|
||||
*
|
||||
* Renesas Solutions Highlander R7780RP support
|
||||
*/
|
||||
|
||||
/* Box specific addresses. */
|
||||
#if defined(CONFIG_SH_R7780MP)
|
||||
#define PA_BCR 0xa4000000 /* FPGA */
|
||||
#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
|
||||
#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
|
||||
#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
|
||||
#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
|
||||
#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
|
||||
#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
|
||||
#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
|
||||
#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
|
||||
#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
|
||||
#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
|
||||
#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
|
||||
#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
|
||||
#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
|
||||
#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
|
||||
#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
|
||||
#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
|
||||
#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
|
||||
#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
|
||||
#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
|
||||
#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
|
||||
#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
|
||||
#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
|
||||
#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
|
||||
#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
|
||||
#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
|
||||
#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
|
||||
#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
|
||||
#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
|
||||
#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
|
||||
#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
|
||||
#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
|
||||
#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
|
||||
#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
|
||||
#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
|
||||
#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
|
||||
#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
|
||||
#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
|
||||
#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
|
||||
#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
|
||||
#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
|
||||
#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
|
||||
#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
|
||||
#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
|
||||
#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
|
||||
#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
|
||||
#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
|
||||
#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
|
||||
#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
|
||||
#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
|
||||
#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
|
||||
#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
|
||||
#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
|
||||
#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
|
||||
#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
|
||||
#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
|
||||
#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
|
||||
#define PA_PMR (PA_BCR+0x0900) /* */
|
||||
|
||||
#define PA_AX88796L 0xa4100400 /* AX88796L Area */
|
||||
#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
|
||||
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
|
||||
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
|
||||
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
|
||||
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
|
||||
|
||||
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
|
||||
|
||||
#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */
|
||||
#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */
|
||||
#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */
|
||||
#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */
|
||||
#define IRQ_CFCARD 1 /* CF Card IRQ */
|
||||
// #define IRQ_CFINST 0 /* CF Card Insert IRQ */
|
||||
#define IRQ_TP 2 /* Touch Panel IRQ */
|
||||
#define IRQ_SCI1 3 /* SCI1 IRQ */
|
||||
#define IRQ_SCI0 4 /* SCI0 IRQ */
|
||||
#define IRQ_2SERIAL 5 /* Serial IRQ */
|
||||
#define IRQ_RTC 6 /* RTC A / B IRQ */
|
||||
#define IRQ_EXTENTION6 7 /* EXT6n IRQ */
|
||||
#define IRQ_EXTENTION5 8 /* EXT5n IRQ */
|
||||
#define IRQ_EXTENTION4 9 /* EXT4n IRQ */
|
||||
#define IRQ_EXTENTION2 10 /* EXT2n IRQ */
|
||||
#define IRQ_EXTENTION1 11 /* EXT1n IRQ */
|
||||
#define IRQ_ONETH 13 /* On board Ethernet IRQ */
|
||||
#define IRQ_PSW 14 /* Push Switch IRQ */
|
||||
|
||||
#else /* R7780RP */
|
||||
|
||||
#define PA_BCR 0xa5000000 /* FPGA */
|
||||
#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
|
||||
#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
|
||||
#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
|
||||
#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
|
||||
#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
|
||||
#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
|
||||
#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
|
||||
#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
|
||||
#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
|
||||
#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
|
||||
#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
|
||||
#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
|
||||
#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
|
||||
#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
|
||||
#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
|
||||
#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
|
||||
#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
|
||||
#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
|
||||
#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
|
||||
#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
|
||||
#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
|
||||
#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
|
||||
#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
|
||||
#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
|
||||
#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
|
||||
#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
|
||||
#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
|
||||
#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
|
||||
#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
|
||||
#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
|
||||
#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
|
||||
#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
|
||||
#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
|
||||
#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
|
||||
#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
|
||||
#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
|
||||
#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
|
||||
#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
|
||||
#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
|
||||
#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
|
||||
#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
|
||||
#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
|
||||
|
||||
#define PA_AX88796L 0xa5800400 /* AX88796L Area */
|
||||
#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
|
||||
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
|
||||
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
|
||||
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
|
||||
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
|
||||
|
||||
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
|
||||
|
||||
#define IRQ_PCISLOT1 0 /* PCI Slot #1 IRQ */
|
||||
#define IRQ_PCISLOT2 1 /* PCI Slot #2 IRQ */
|
||||
#define IRQ_PCISLOT3 2 /* PCI Slot #3 IRQ */
|
||||
#define IRQ_PCISLOT4 3 /* PCI Slot #4 IRQ */
|
||||
#define IRQ_CFCARD 4 /* CF Card IRQ */
|
||||
#define IRQ_CFINST 5 /* CF Card Insert IRQ */
|
||||
#define IRQ_M66596 6 /* M66596 IRQ */
|
||||
#define IRQ_SDCARD 7 /* SD Card IRQ */
|
||||
#define IRQ_TUCHPANEL 8 /* Touch Panel IRQ */
|
||||
#define IRQ_SCI 9 /* SCI IRQ */
|
||||
#define IRQ_2SERIAL 10 /* Serial IRQ */
|
||||
#define IRQ_EXTENTION 11 /* EXTn IRQ */
|
||||
#define IRQ_ONETH 12 /* On board Ethernet IRQ */
|
||||
#define IRQ_PSW 13 /* Push Switch IRQ */
|
||||
#define IRQ_ZIGBEE 14 /* Ziggbee IO IRQ */
|
||||
|
||||
#endif /* CONFIG_SH_R7780MP */
|
||||
|
||||
#define __IO_PREFIX r7780rp
|
||||
#include <asm/io_generic.h>
|
||||
|
||||
#endif /* __ASM_SH_RENESAS_R7780RP */
|
||||
@ -41,8 +41,6 @@
|
||||
|
||||
#define PA_AX88796L 0xaa000400 /* AX88796L Area */
|
||||
#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
|
||||
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
|
||||
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
|
||||
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
|
||||
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user