clk: sparx5: Add Sparx5 SoC DPLL clock driver
This adds a device driver for the Sparx5 SoC DPLL clock Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200727084211.6632-9-lars.povlsen@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Lars Povlsen
Stephen Boyd
parent
4299f85a67
commit
53727eb6b3
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@ -28,6 +28,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
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obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
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obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
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obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
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obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
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obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
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obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
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obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
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295
drivers/clk/clk-sparx5.c
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295
drivers/clk/clk-sparx5.c
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@ -0,0 +1,295 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Microchip Sparx5 SoC Clock driver.
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*
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* Copyright (c) 2019 Microchip Inc.
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*
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* Author: Lars Povlsen <lars.povlsen@microchip.com>
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/bitfield.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/microchip,sparx5.h>
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#define PLL_DIV GENMASK(7, 0)
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#define PLL_PRE_DIV GENMASK(10, 8)
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#define PLL_ROT_DIR BIT(11)
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#define PLL_ROT_SEL GENMASK(13, 12)
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#define PLL_ROT_ENA BIT(14)
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#define PLL_CLK_ENA BIT(15)
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#define MAX_SEL 4
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#define MAX_PRE BIT(3)
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static const u8 sel_rates[MAX_SEL] = { 0, 2*8, 2*4, 2*2 };
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static const char *clk_names[N_CLOCKS] = {
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"core", "ddr", "cpu2", "arm2",
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"aux1", "aux2", "aux3", "aux4",
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"synce",
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};
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struct s5_hw_clk {
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struct clk_hw hw;
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void __iomem *reg;
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};
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struct s5_clk_data {
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void __iomem *base;
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struct s5_hw_clk s5_hw[N_CLOCKS];
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};
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struct s5_pll_conf {
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unsigned long freq;
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u8 div;
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bool rot_ena;
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u8 rot_sel;
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u8 rot_dir;
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u8 pre_div;
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};
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#define to_s5_pll(hw) container_of(hw, struct s5_hw_clk, hw)
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static unsigned long s5_calc_freq(unsigned long parent_rate,
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const struct s5_pll_conf *conf)
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{
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unsigned long rate = parent_rate / conf->div;
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if (conf->rot_ena) {
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int sign = conf->rot_dir ? -1 : 1;
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int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div);
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int divb = divt + sign;
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rate = mult_frac(rate, divt, divb);
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rate = roundup(rate, 1000);
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}
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return rate;
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}
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static void s5_search_fractional(unsigned long rate,
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unsigned long parent_rate,
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int div,
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struct s5_pll_conf *conf)
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{
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struct s5_pll_conf best;
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ulong cur_offset, best_offset = rate;
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int d, i, j;
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memset(conf, 0, sizeof(*conf));
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conf->div = div;
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conf->rot_ena = 1; /* Fractional rate */
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for (d = 0; best_offset > 0 && d <= 1 ; d++) {
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conf->rot_dir = !!d;
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for (i = 0; best_offset > 0 && i < MAX_PRE; i++) {
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conf->pre_div = i;
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for (j = 1; best_offset > 0 && j < MAX_SEL; j++) {
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conf->rot_sel = j;
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conf->freq = s5_calc_freq(parent_rate, conf);
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cur_offset = abs(rate - conf->freq);
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if (cur_offset < best_offset) {
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best_offset = cur_offset;
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best = *conf;
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}
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}
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}
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}
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/* Best match */
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*conf = best;
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}
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static unsigned long s5_calc_params(unsigned long rate,
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unsigned long parent_rate,
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struct s5_pll_conf *conf)
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{
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if (parent_rate % rate) {
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struct s5_pll_conf alt1, alt2;
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int div;
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div = DIV_ROUND_CLOSEST_ULL(parent_rate, rate);
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s5_search_fractional(rate, parent_rate, div, &alt1);
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/* Straight match? */
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if (alt1.freq == rate) {
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*conf = alt1;
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} else {
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/* Try without rounding divider */
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div = parent_rate / rate;
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if (div != alt1.div) {
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s5_search_fractional(rate, parent_rate, div,
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&alt2);
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/* Select the better match */
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if (abs(rate - alt1.freq) <
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abs(rate - alt2.freq))
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*conf = alt1;
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else
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*conf = alt2;
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}
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}
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} else {
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/* Straight fit */
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memset(conf, 0, sizeof(*conf));
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conf->div = parent_rate / rate;
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}
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return conf->freq;
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}
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static int s5_pll_enable(struct clk_hw *hw)
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{
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struct s5_hw_clk *pll = to_s5_pll(hw);
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u32 val = readl(pll->reg);
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val |= PLL_CLK_ENA;
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writel(val, pll->reg);
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return 0;
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}
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static void s5_pll_disable(struct clk_hw *hw)
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{
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struct s5_hw_clk *pll = to_s5_pll(hw);
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u32 val = readl(pll->reg);
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val &= ~PLL_CLK_ENA;
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writel(val, pll->reg);
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}
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static int s5_pll_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct s5_hw_clk *pll = to_s5_pll(hw);
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struct s5_pll_conf conf;
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unsigned long eff_rate;
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u32 val;
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eff_rate = s5_calc_params(rate, parent_rate, &conf);
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if (eff_rate != rate)
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return -EOPNOTSUPP;
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val = readl(pll->reg) & PLL_CLK_ENA;
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val |= FIELD_PREP(PLL_DIV, conf.div);
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if (conf.rot_ena) {
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val |= PLL_ROT_ENA;
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val |= FIELD_PREP(PLL_ROT_SEL, conf.rot_sel);
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val |= FIELD_PREP(PLL_PRE_DIV, conf.pre_div);
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if (conf.rot_dir)
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val |= PLL_ROT_DIR;
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}
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writel(val, pll->reg);
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return 0;
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}
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static unsigned long s5_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct s5_hw_clk *pll = to_s5_pll(hw);
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struct s5_pll_conf conf;
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u32 val;
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val = readl(pll->reg);
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if (val & PLL_CLK_ENA) {
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conf.div = FIELD_GET(PLL_DIV, val);
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conf.pre_div = FIELD_GET(PLL_PRE_DIV, val);
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conf.rot_ena = FIELD_GET(PLL_ROT_ENA, val);
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conf.rot_dir = FIELD_GET(PLL_ROT_DIR, val);
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conf.rot_sel = FIELD_GET(PLL_ROT_SEL, val);
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conf.freq = s5_calc_freq(parent_rate, &conf);
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} else {
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conf.freq = 0;
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}
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return conf.freq;
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}
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static long s5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct s5_pll_conf conf;
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return s5_calc_params(rate, *parent_rate, &conf);
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}
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static const struct clk_ops s5_pll_ops = {
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.enable = s5_pll_enable,
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.disable = s5_pll_disable,
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.set_rate = s5_pll_set_rate,
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.round_rate = s5_pll_round_rate,
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.recalc_rate = s5_pll_recalc_rate,
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};
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static struct clk_hw *s5_clk_hw_get(struct of_phandle_args *clkspec, void *data)
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{
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struct s5_clk_data *s5_clk = data;
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unsigned int idx = clkspec->args[0];
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if (idx >= N_CLOCKS) {
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pr_err("%s: invalid index %u\n", __func__, idx);
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return ERR_PTR(-EINVAL);
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}
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return &s5_clk->s5_hw[idx].hw;
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}
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static int s5_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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int i, ret;
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struct s5_clk_data *s5_clk;
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struct clk_parent_data pdata = { .index = 0 };
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struct clk_init_data init = {
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.ops = &s5_pll_ops,
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.num_parents = 1,
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.parent_data = &pdata,
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};
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s5_clk = devm_kzalloc(dev, sizeof(*s5_clk), GFP_KERNEL);
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if (!s5_clk)
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return -ENOMEM;
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s5_clk->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(s5_clk->base))
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return PTR_ERR(s5_clk->base);
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for (i = 0; i < N_CLOCKS; i++) {
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struct s5_hw_clk *s5_hw = &s5_clk->s5_hw[i];
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init.name = clk_names[i];
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s5_hw->reg = s5_clk->base + (i * 4);
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s5_hw->hw.init = &init;
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ret = devm_clk_hw_register(dev, &s5_hw->hw);
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if (ret) {
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dev_err(dev, "failed to register %s clock\n",
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init.name);
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return ret;
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}
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}
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return devm_of_clk_add_hw_provider(dev, s5_clk_hw_get, s5_clk);
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}
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static const struct of_device_id s5_clk_dt_ids[] = {
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{ .compatible = "microchip,sparx5-dpll", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, s5_clk_dt_ids);
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static struct platform_driver s5_clk_driver = {
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.probe = s5_clk_probe,
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.driver = {
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.name = "sparx5-clk",
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.of_match_table = s5_clk_dt_ids,
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},
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};
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builtin_platform_driver(s5_clk_driver);
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