Merge branch 'sdhci_omap' into next
Merge immutable branch for sdhci-omap to add UHS/HS200 mode support. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Ulf Hansson
commit
5581cfcdcc
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@ -4,7 +4,14 @@ Refer to mmc.txt for standard MMC bindings.
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Required properties:
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- compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
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Should be "ti,k2g-sdhci" for K2G
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- ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1
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(Not required for K2G).
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- pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50",
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"ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
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"ddr_1_8v-rev11", "ddr_1_8v" or "ddr_3_3v", "hs200_1_8v-rev11",
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"hs200_1_8v",
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- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
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Example:
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mmc1: mmc@4809c000 {
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@ -26,6 +26,7 @@
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/sys_soc.h>
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#include "sdhci-pltfm.h"
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@ -35,6 +36,7 @@
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#define CON_DDR BIT(19)
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#define CON_CLKEXTFREE BIT(16)
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#define CON_PADEN BIT(15)
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#define CON_CTPL BIT(11)
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#define CON_INIT BIT(1)
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#define CON_OD BIT(0)
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@ -100,6 +102,7 @@ struct sdhci_omap_data {
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};
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struct sdhci_omap_host {
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char *version;
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void __iomem *base;
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struct device *dev;
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struct regulator *pbias;
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@ -224,6 +227,23 @@ static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
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}
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}
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static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
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u32 reg;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
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if (enable)
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reg |= (CON_CTPL | CON_CLKEXTFREE);
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else
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reg &= ~(CON_CTPL | CON_CLKEXTFREE);
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sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
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sdhci_enable_sdio_irq(mmc, enable);
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}
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static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
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int count)
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{
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@ -713,10 +733,15 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = {
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SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
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.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
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SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_RSP_136_HAS_CRC,
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SDHCI_QUIRK2_RSP_136_HAS_CRC |
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SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
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.ops = &sdhci_omap_ops,
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};
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static const struct sdhci_omap_data k2g_data = {
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.offset = 0x200,
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};
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static const struct sdhci_omap_data dra7_data = {
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.offset = 0x200,
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.flags = SDHCI_OMAP_REQUIRE_IODELAY,
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@ -724,6 +749,7 @@ static const struct sdhci_omap_data dra7_data = {
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static const struct of_device_id omap_sdhci_match[] = {
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{ .compatible = "ti,dra7-sdhci", .data = &dra7_data },
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{ .compatible = "ti,k2g-sdhci", .data = &k2g_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, omap_sdhci_match);
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@ -733,12 +759,21 @@ static struct pinctrl_state
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u32 *caps, u32 capmask)
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{
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struct device *dev = omap_host->dev;
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char *version = omap_host->version;
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struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
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char str[20];
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if (!(*caps & capmask))
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goto ret;
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pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
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if (version) {
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snprintf(str, 20, "%s-%s", mode, version);
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pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
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}
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if (IS_ERR(pinctrl_state))
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pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
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if (IS_ERR(pinctrl_state)) {
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dev_err(dev, "no pinctrl state for %s mode", mode);
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*caps &= ~capmask;
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@ -807,8 +842,15 @@ static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
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MMC_CAP_1_8V_DDR);
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if (!IS_ERR(state))
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if (!IS_ERR(state)) {
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pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
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} else {
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
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caps,
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MMC_CAP_3_3V_DDR);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
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}
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
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MMC_CAP_SD_HIGHSPEED);
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@ -830,6 +872,16 @@ static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
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return 0;
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}
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static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
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{
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.machine = "DRA7[45]*",
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.revision = "ES1.[01]",
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},
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{
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/* sentinel */
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}
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};
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static int sdhci_omap_probe(struct platform_device *pdev)
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{
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int ret;
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@ -841,6 +893,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
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struct mmc_host *mmc;
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const struct of_device_id *match;
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struct sdhci_omap_data *data;
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const struct soc_device_attribute *soc;
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match = of_match_device(omap_sdhci_match, dev);
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if (!match)
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@ -871,10 +924,22 @@ static int sdhci_omap_probe(struct platform_device *pdev)
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host->ioaddr += offset;
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mmc = host->mmc;
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sdhci_get_of_property(pdev);
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ret = mmc_of_parse(mmc);
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if (ret)
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goto err_pltfm_free;
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soc = soc_device_match(sdhci_omap_soc_devices);
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if (soc) {
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omap_host->version = "rev11";
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if (!strcmp(dev_name(dev), "4809c000.mmc"))
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mmc->f_max = 96000000;
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if (!strcmp(dev_name(dev), "480b4000.mmc"))
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mmc->f_max = 48000000;
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if (!strcmp(dev_name(dev), "480ad000.mmc"))
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mmc->f_max = 48000000;
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}
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pltfm_host->clk = devm_clk_get(dev, "fck");
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if (IS_ERR(pltfm_host->clk)) {
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ret = PTR_ERR(pltfm_host->clk);
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@ -916,26 +981,31 @@ static int sdhci_omap_probe(struct platform_device *pdev)
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goto err_put_sync;
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}
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ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
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if (ret)
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goto err_put_sync;
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host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
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host->mmc_host_ops.start_signal_voltage_switch =
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sdhci_omap_start_signal_voltage_switch;
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host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
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host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
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host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
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host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
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sdhci_read_caps(host);
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host->caps |= SDHCI_CAN_DO_ADMA2;
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ret = sdhci_add_host(host);
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ret = sdhci_setup_host(host);
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if (ret)
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goto err_put_sync;
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ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
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if (ret)
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goto err_cleanup_host;
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ret = __sdhci_add_host(host);
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if (ret)
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goto err_cleanup_host;
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return 0;
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err_cleanup_host:
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sdhci_cleanup_host(host);
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err_put_sync:
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pm_runtime_put_sync(dev);
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@ -709,29 +709,16 @@ static u32 sdhci_sdma_address(struct sdhci_host *host)
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return sg_dma_address(host->data->sg);
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}
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static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
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static unsigned int sdhci_target_timeout(struct sdhci_host *host,
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struct mmc_command *cmd,
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struct mmc_data *data)
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{
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u8 count;
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struct mmc_data *data = cmd->data;
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unsigned target_timeout, current_timeout;
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/*
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* If the host controller provides us with an incorrect timeout
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* value, just skip the check and use 0xE. The hardware may take
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* longer to time out, but that's much better than having a too-short
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* timeout value.
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*/
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if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
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return 0xE;
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/* Unspecified timeout, assume max */
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if (!data && !cmd->busy_timeout)
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return 0xE;
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unsigned int target_timeout;
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/* timeout in us */
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if (!data)
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if (!data) {
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target_timeout = cmd->busy_timeout * 1000;
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else {
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} else {
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target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
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if (host->clock && data->timeout_clks) {
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unsigned long long val;
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@ -748,6 +735,67 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
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}
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}
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return target_timeout;
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}
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static void sdhci_calc_sw_timeout(struct sdhci_host *host,
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struct mmc_command *cmd)
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{
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struct mmc_data *data = cmd->data;
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struct mmc_host *mmc = host->mmc;
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struct mmc_ios *ios = &mmc->ios;
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unsigned char bus_width = 1 << ios->bus_width;
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unsigned int blksz;
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unsigned int freq;
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u64 target_timeout;
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u64 transfer_time;
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target_timeout = sdhci_target_timeout(host, cmd, data);
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target_timeout *= NSEC_PER_USEC;
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if (data) {
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blksz = data->blksz;
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freq = host->mmc->actual_clock ? : host->clock;
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transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
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do_div(transfer_time, freq);
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/* multiply by '2' to account for any unknowns */
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transfer_time = transfer_time * 2;
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/* calculate timeout for the entire data */
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host->data_timeout = data->blocks * target_timeout +
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transfer_time;
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} else {
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host->data_timeout = target_timeout;
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}
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|
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if (host->data_timeout)
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host->data_timeout += MMC_CMD_TRANSFER_TIME;
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}
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static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
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bool *too_big)
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{
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u8 count;
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struct mmc_data *data = cmd->data;
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unsigned target_timeout, current_timeout;
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|
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*too_big = true;
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/*
|
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* If the host controller provides us with an incorrect timeout
|
||||
* value, just skip the check and use 0xE. The hardware may take
|
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* longer to time out, but that's much better than having a too-short
|
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* timeout value.
|
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*/
|
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if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
|
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return 0xE;
|
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|
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/* Unspecified timeout, assume max */
|
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if (!data && !cmd->busy_timeout)
|
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return 0xE;
|
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|
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/* timeout in us */
|
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target_timeout = sdhci_target_timeout(host, cmd, data);
|
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|
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/*
|
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* Figure out needed cycles.
|
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* We do this in steps in order to fit inside a 32 bit int.
|
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|
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@ -768,9 +816,12 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
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}
|
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|
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if (count >= 0xF) {
|
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DBG("Too large timeout 0x%x requested for CMD%d!\n",
|
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count, cmd->opcode);
|
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if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
|
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DBG("Too large timeout 0x%x requested for CMD%d!\n",
|
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count, cmd->opcode);
|
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count = 0xE;
|
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} else {
|
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*too_big = false;
|
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}
|
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|
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return count;
|
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|
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@ -790,6 +841,16 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
|
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sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
||||
}
|
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|
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static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
|
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{
|
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if (enable)
|
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host->ier |= SDHCI_INT_DATA_TIMEOUT;
|
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else
|
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host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
|
||||
sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
|
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sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
|
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}
|
||||
|
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static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
|
||||
{
|
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u8 count;
|
||||
|
|
@ -797,7 +858,18 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
|
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if (host->ops->set_timeout) {
|
||||
host->ops->set_timeout(host, cmd);
|
||||
} else {
|
||||
count = sdhci_calc_timeout(host, cmd);
|
||||
bool too_big = false;
|
||||
|
||||
count = sdhci_calc_timeout(host, cmd, &too_big);
|
||||
|
||||
if (too_big &&
|
||||
host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
|
||||
sdhci_calc_sw_timeout(host, cmd);
|
||||
sdhci_set_data_timeout_irq(host, false);
|
||||
} else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
|
||||
sdhci_set_data_timeout_irq(host, true);
|
||||
}
|
||||
|
||||
sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
|
||||
}
|
||||
}
|
||||
|
|
@ -807,6 +879,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
|
|||
u8 ctrl;
|
||||
struct mmc_data *data = cmd->data;
|
||||
|
||||
host->data_timeout = 0;
|
||||
|
||||
if (sdhci_data_line_cmd(cmd))
|
||||
sdhci_set_timeout(host, cmd);
|
||||
|
||||
|
|
@ -1160,13 +1234,6 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
|
|||
mdelay(1);
|
||||
}
|
||||
|
||||
timeout = jiffies;
|
||||
if (!cmd->data && cmd->busy_timeout > 9000)
|
||||
timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
|
||||
else
|
||||
timeout += 10 * HZ;
|
||||
sdhci_mod_timer(host, cmd->mrq, timeout);
|
||||
|
||||
host->cmd = cmd;
|
||||
if (sdhci_data_line_cmd(cmd)) {
|
||||
WARN_ON(host->data_cmd);
|
||||
|
|
@ -1206,6 +1273,15 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
|
|||
cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
|
||||
flags |= SDHCI_CMD_DATA;
|
||||
|
||||
timeout = jiffies;
|
||||
if (host->data_timeout)
|
||||
timeout += nsecs_to_jiffies(host->data_timeout);
|
||||
else if (!cmd->data && cmd->busy_timeout > 9000)
|
||||
timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
|
||||
else
|
||||
timeout += 10 * HZ;
|
||||
sdhci_mod_timer(host, cmd->mrq, timeout);
|
||||
|
||||
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sdhci_send_command);
|
||||
|
|
@ -3616,6 +3692,10 @@ int sdhci_setup_host(struct sdhci_host *host)
|
|||
mmc->max_busy_timeout /= host->timeout_clk;
|
||||
}
|
||||
|
||||
if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
|
||||
!host->ops->get_max_timeout_count)
|
||||
mmc->max_busy_timeout = 0;
|
||||
|
||||
mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
|
||||
mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
|
||||
|
||||
|
|
@ -3672,6 +3752,16 @@ int sdhci_setup_host(struct sdhci_host *host)
|
|||
if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
|
||||
host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
|
||||
SDHCI_SUPPORT_DDR50);
|
||||
/*
|
||||
* The SDHCI controller in a SoC might support HS200/HS400
|
||||
* (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
|
||||
* but if the board is modeled such that the IO lines are not
|
||||
* connected to 1.8v then HS200/HS400 cannot be supported.
|
||||
* Disable HS200/HS400 if the board does not have 1.8v connected
|
||||
* to the IO lines. (Applicable for other modes in 1.8v)
|
||||
*/
|
||||
mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
|
||||
mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
|
||||
}
|
||||
|
||||
/* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
|
||||
|
|
|
|||
|
|
@ -332,6 +332,14 @@ struct sdhci_adma2_64_desc {
|
|||
/* Allow for a a command request and a data request at the same time */
|
||||
#define SDHCI_MAX_MRQS 2
|
||||
|
||||
/*
|
||||
* 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
|
||||
* However since the start time of the command, the time between
|
||||
* command and response, and the time between response and start of data is
|
||||
* not known, set the command transfer time to 10ms.
|
||||
*/
|
||||
#define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */
|
||||
|
||||
enum sdhci_cookie {
|
||||
COOKIE_UNMAPPED,
|
||||
COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
|
||||
|
|
@ -437,6 +445,11 @@ struct sdhci_host {
|
|||
#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
|
||||
/* Controller has CRC in 136 bit Command Response */
|
||||
#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
|
||||
/*
|
||||
* Disable HW timeout if the requested timeout is more than the maximum
|
||||
* obtainable timeout.
|
||||
*/
|
||||
#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17)
|
||||
|
||||
int irq; /* Device IRQ */
|
||||
void __iomem *ioaddr; /* Mapped address */
|
||||
|
|
@ -550,6 +563,8 @@ struct sdhci_host {
|
|||
/* Host SDMA buffer boundary. */
|
||||
u32 sdma_boundary;
|
||||
|
||||
u64 data_timeout;
|
||||
|
||||
unsigned long private[0] ____cacheline_aligned;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -320,6 +320,9 @@ struct mmc_host {
|
|||
#define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */
|
||||
#define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */
|
||||
#define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */
|
||||
#define MMC_CAP_UHS (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | \
|
||||
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | \
|
||||
MMC_CAP_UHS_DDR50)
|
||||
/* (1 << 21) is free for reuse */
|
||||
#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
|
||||
#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
|
||||
|
|
@ -345,6 +348,7 @@ struct mmc_host {
|
|||
#define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */
|
||||
#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \
|
||||
MMC_CAP2_HS400_1_2V)
|
||||
#define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)
|
||||
#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
|
||||
#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
|
||||
#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user