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drm/radeon: make ring rptr and wptr register offsets variable

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Every ring seems to have the concept of read and
write pointers. Make the register offset variable
so we can use the functions for different types of rings.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Christian König 2011-10-13 12:48:45 +02:00 committed by Dave Airlie
parent 7b1f2485db
commit 5596a9db15
9 changed files with 29 additions and 52 deletions
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3
drivers/gpu/drm/radeon/evergreen.c
View File

@ -3120,7 +3120,8 @@ static int evergreen_startup(struct radeon_device *rdev)
}
evergreen_irq_set(rdev);
r = radeon_ring_init(rdev, cp, cp->ring_size);
r = radeon_ring_init(rdev, cp, cp->ring_size, RADEON_WB_CP_RPTR_OFFSET,
R600_CP_RB_RPTR, R600_CP_RB_WPTR);
if (r)
return r;
r = evergreen_cp_load_microcode(rdev);

5
drivers/gpu/drm/radeon/ni.c
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@ -1273,7 +1273,7 @@ bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
radeon_ring_unlock_commit(rdev, cp);
}
/* XXX deal with CP0,1,2 */
cp->rptr = RREG32(CP_RB0_RPTR);
cp->rptr = RREG32(cp->rptr_reg);
return r100_gpu_cp_is_lockup(rdev, lockup, cp);
}
@ -1393,7 +1393,8 @@ static int cayman_startup(struct radeon_device *rdev)
}
evergreen_irq_set(rdev);
r = radeon_ring_init(rdev, cp, cp->ring_size);
r = radeon_ring_init(rdev, cp, cp->ring_size, RADEON_WB_CP_RPTR_OFFSET,
CP_RB0_RPTR, CP_RB0_WPTR);
if (r)
return r;
r = cayman_cp_load_microcode(rdev);

12
drivers/gpu/drm/radeon/r100.c
View File

@ -1074,7 +1074,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
rb_bufsz = drm_order(ring_size / 8);
ring_size = (1 << (rb_bufsz + 1)) * 4;
r100_cp_load_microcode(rdev);
r = radeon_ring_init(rdev, cp, ring_size);
r = radeon_ring_init(rdev, cp, ring_size, RADEON_WB_CP_RPTR_OFFSET,
RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR);
if (r) {
return r;
}
@ -1179,13 +1180,6 @@ void r100_cp_disable(struct radeon_device *rdev)
}
}
void r100_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp)
{
WREG32(RADEON_CP_RB_WPTR, cp->wptr);
(void)RREG32(RADEON_CP_RB_WPTR);
}
/*
* CS functions
*/
@ -2184,7 +2178,7 @@ bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
radeon_ring_write(cp, 0x80000000);
radeon_ring_unlock_commit(rdev, cp);
}
cp->rptr = RREG32(RADEON_CP_RB_RPTR);
cp->rptr = RREG32(cp->rptr_reg);
return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, cp);
}

12
drivers/gpu/drm/radeon/r600.c
View File

@ -1372,7 +1372,7 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
radeon_ring_write(cp, 0x80000000);
radeon_ring_unlock_commit(rdev, cp);
}
cp->rptr = RREG32(R600_CP_RB_RPTR);
cp->rptr = RREG32(cp->rptr_reg);
return r100_gpu_cp_is_lockup(rdev, lockup, cp);
}
@ -2234,12 +2234,6 @@ int r600_cp_resume(struct radeon_device *rdev)
return 0;
}
void r600_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp)
{
WREG32(CP_RB_WPTR, cp->wptr);
(void)RREG32(CP_RB_WPTR);
}
void r600_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size)
{
u32 rb_bufsz;
@ -2474,7 +2468,9 @@ int r600_startup(struct radeon_device *rdev)
}
r600_irq_set(rdev);
r = radeon_ring_init(rdev, cp, cp->ring_size);
r = radeon_ring_init(rdev, cp, cp->ring_size, RADEON_WB_CP_RPTR_OFFSET,
R600_CP_RB_RPTR, R600_CP_RB_WPTR);
if (r)
return r;
r = r600_cp_load_microcode(rdev);

8
drivers/gpu/drm/radeon/radeon.h
View File

@ -525,8 +525,11 @@ struct radeon_cp {
struct radeon_bo *ring_obj;
volatile uint32_t *ring;
unsigned rptr;
unsigned rptr_offs;
unsigned rptr_reg;
unsigned wptr;
unsigned wptr_old;
unsigned wptr_reg;
unsigned ring_size;
unsigned ring_free_dw;
int count_dw;
@ -602,7 +605,8 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_cp *cp);
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_cp *cp);
void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_cp *cp);
int radeon_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size);
int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size,
unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg);
void radeon_ring_fini(struct radeon_device *rdev, struct radeon_cp *cp);
@ -939,7 +943,6 @@ struct radeon_asic {
int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
void (*cp_fini)(struct radeon_device *rdev);
void (*cp_disable)(struct radeon_device *rdev);
void (*cp_commit)(struct radeon_device *rdev, struct radeon_cp *cp);
void (*ring_start)(struct radeon_device *rdev);
int (*ring_test)(struct radeon_device *rdev, struct radeon_cp *cp);
void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
@ -1491,7 +1494,6 @@ void radeon_ring_write(struct radeon_cp *cp, uint32_t v);
#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
#define radeon_cp_commit(rdev, cp) (rdev)->asic->cp_commit((rdev), (cp))
#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
#define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))

17
drivers/gpu/drm/radeon/radeon_asic.c
View File

@ -138,7 +138,6 @@ static struct radeon_asic r100_asic = {
.asic_reset = &r100_asic_reset,
.gart_tlb_flush = &r100_pci_gart_tlb_flush,
.gart_set_page = &r100_pci_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &r100_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -187,7 +186,6 @@ static struct radeon_asic r200_asic = {
.asic_reset = &r100_asic_reset,
.gart_tlb_flush = &r100_pci_gart_tlb_flush,
.gart_set_page = &r100_pci_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &r100_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -235,7 +233,6 @@ static struct radeon_asic r300_asic = {
.asic_reset = &r300_asic_reset,
.gart_tlb_flush = &r100_pci_gart_tlb_flush,
.gart_set_page = &r100_pci_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -284,7 +281,6 @@ static struct radeon_asic r300_asic_pcie = {
.asic_reset = &r300_asic_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -332,7 +328,6 @@ static struct radeon_asic r420_asic = {
.asic_reset = &r300_asic_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -381,7 +376,6 @@ static struct radeon_asic rs400_asic = {
.asic_reset = &r300_asic_reset,
.gart_tlb_flush = &rs400_gart_tlb_flush,
.gart_set_page = &rs400_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -430,7 +424,6 @@ static struct radeon_asic rs600_asic = {
.asic_reset = &rs600_asic_reset,
.gart_tlb_flush = &rs600_gart_tlb_flush,
.gart_set_page = &rs600_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -479,7 +472,6 @@ static struct radeon_asic rs690_asic = {
.asic_reset = &rs600_asic_reset,
.gart_tlb_flush = &rs400_gart_tlb_flush,
.gart_set_page = &rs400_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &r300_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -528,7 +520,6 @@ static struct radeon_asic rv515_asic = {
.asic_reset = &rs600_asic_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &rv515_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -577,7 +568,6 @@ static struct radeon_asic r520_asic = {
.asic_reset = &rs600_asic_reset,
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
.gart_set_page = &rv370_pcie_gart_set_page,
.cp_commit = &r100_cp_commit,
.ring_start = &rv515_ring_start,
.ring_test = &r100_ring_test,
.ring_ib_execute = &r100_ring_ib_execute,
@ -621,7 +611,6 @@ static struct radeon_asic r600_asic = {
.fini = &r600_fini,
.suspend = &r600_suspend,
.resume = &r600_resume,
.cp_commit = &r600_cp_commit,
.vga_set_state = &r600_vga_set_state,
.gpu_is_lockup = &r600_gpu_is_lockup,
.asic_reset = &r600_asic_reset,
@ -669,7 +658,6 @@ static struct radeon_asic rs780_asic = {
.fini = &r600_fini,
.suspend = &r600_suspend,
.resume = &r600_resume,
.cp_commit = &r600_cp_commit,
.gpu_is_lockup = &r600_gpu_is_lockup,
.vga_set_state = &r600_vga_set_state,
.asic_reset = &r600_asic_reset,
@ -717,7 +705,6 @@ static struct radeon_asic rv770_asic = {
.fini = &rv770_fini,
.suspend = &rv770_suspend,
.resume = &rv770_resume,
.cp_commit = &r600_cp_commit,
.asic_reset = &r600_asic_reset,
.gpu_is_lockup = &r600_gpu_is_lockup,
.vga_set_state = &r600_vga_set_state,
@ -765,7 +752,6 @@ static struct radeon_asic evergreen_asic = {
.fini = &evergreen_fini,
.suspend = &evergreen_suspend,
.resume = &evergreen_resume,
.cp_commit = &r600_cp_commit,
.gpu_is_lockup = &evergreen_gpu_is_lockup,
.asic_reset = &evergreen_asic_reset,
.vga_set_state = &r600_vga_set_state,
@ -813,7 +799,6 @@ static struct radeon_asic sumo_asic = {
.fini = &evergreen_fini,
.suspend = &evergreen_suspend,
.resume = &evergreen_resume,
.cp_commit = &r600_cp_commit,
.gpu_is_lockup = &evergreen_gpu_is_lockup,
.asic_reset = &evergreen_asic_reset,
.vga_set_state = &r600_vga_set_state,
@ -861,7 +846,6 @@ static struct radeon_asic btc_asic = {
.fini = &evergreen_fini,
.suspend = &evergreen_suspend,
.resume = &evergreen_resume,
.cp_commit = &r600_cp_commit,
.gpu_is_lockup = &evergreen_gpu_is_lockup,
.asic_reset = &evergreen_asic_reset,
.vga_set_state = &r600_vga_set_state,
@ -909,7 +893,6 @@ static struct radeon_asic cayman_asic = {
.fini = &cayman_fini,
.suspend = &cayman_suspend,
.resume = &cayman_resume,
.cp_commit = &r600_cp_commit,
.gpu_is_lockup = &cayman_gpu_is_lockup,
.asic_reset = &cayman_asic_reset,
.vga_set_state = &r600_vga_set_state,

2
drivers/gpu/drm/radeon/radeon_asic.h
View File

@ -63,7 +63,6 @@ int r100_asic_reset(struct radeon_device *rdev);
u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
void r100_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp);
void r100_ring_start(struct radeon_device *rdev);
int r100_irq_set(struct radeon_device *rdev);
int r100_irq_process(struct radeon_device *rdev);
@ -297,7 +296,6 @@ int r600_resume(struct radeon_device *rdev);
void r600_vga_set_state(struct radeon_device *rdev, bool state);
int r600_wb_init(struct radeon_device *rdev);
void r600_wb_fini(struct radeon_device *rdev);
void r600_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp);
void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);

19
drivers/gpu/drm/radeon/radeon_ring.c
View File

@ -287,13 +287,9 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_cp *cp)
{
if (rdev->wb.enabled)
rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]);
else {
if (rdev->family >= CHIP_R600)
rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
else
rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
}
cp->rptr = le32_to_cpu(rdev->wb.wb[cp->rptr_offs/4]);
else
cp->rptr = RREG32(cp->rptr_reg);
/* This works because ring_size is a power of 2 */
cp->ring_free_dw = (cp->rptr + (cp->ring_size / 4));
cp->ring_free_dw -= cp->wptr;
@ -350,7 +346,8 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_cp *cp)
radeon_ring_write(cp, 2 << 30);
}
DRM_MEMORYBARRIER();
radeon_cp_commit(rdev, cp);
WREG32(cp->wptr_reg, cp->wptr);
(void)RREG32(cp->wptr_reg);
}
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_cp *cp)
@ -365,11 +362,15 @@ void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_cp *cp)
mutex_unlock(&cp->mutex);
}
int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size)
int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size,
unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg)
{
int r;
cp->ring_size = ring_size;
cp->rptr_offs = rptr_offs;
cp->rptr_reg = rptr_reg;
cp->wptr_reg = wptr_reg;
/* Allocate ring buffer */
if (cp->ring_obj == NULL) {
r = radeon_bo_create(rdev, cp->ring_size, PAGE_SIZE, true,

3
drivers/gpu/drm/radeon/rv770.c
View File

@ -1092,7 +1092,8 @@ static int rv770_startup(struct radeon_device *rdev)
}
r600_irq_set(rdev);
r = radeon_ring_init(rdev, cp, cp->ring_size);
r = radeon_ring_init(rdev, cp, cp->ring_size, RADEON_WB_CP_RPTR_OFFSET,
R600_CP_RB_RPTR, R600_CP_RB_WPTR);
if (r)
return r;
r = rv770_cp_load_microcode(rdev);