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pdc202xx_new: PLL detection fix

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Fix a bitmask typo in the pdc202xx_new PLL frequency detection code
which causes it to truncate an intermediate difference to 26 bits
instead of the correct 30 bits (the PLL's bitwidth).

Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Mikael Pettersson 2007-09-11 22:28:37 +02:00 committed by Bartlomiej Zolnierkiewicz
parent 58e47bb176
commit 56fe23d5a7
1 changed files with 1 additions and 1 deletions
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2
drivers/ide/pci/pdc202xx_new.c
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@ -341,7 +341,7 @@ static long __devinit detect_pll_input_clock(unsigned long dma_base)
*/
usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
(end_time.tv_usec - start_time.tv_usec);
pll_input = ((start_count - end_count) & 0x3ffffff) / 10 *
pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
(10000000 / usec_elapsed);
DBG("start[%ld] end[%ld]\n", start_count, end_count);