drm/radeon: fix hdmi audio on DCE3.0/3.1 asics
These asics seem to use a mix of the DCE2.x and DCE3.2 audio interfaces despite what the register spec says. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=69729 https://bugs.freedesktop.org/show_bug.cgi?id=69671 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -257,10 +257,7 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
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* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
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*/
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if (ASIC_IS_DCE3(rdev)) {
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/* according to the reg specs, this should DCE3.2 only, but in
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* practice it seems to cover DCE3.0 as well.
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*/
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if (ASIC_IS_DCE32(rdev)) {
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if (dig->dig_encoder == 0) {
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dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
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dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
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@ -276,8 +273,21 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
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WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
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WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
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}
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} else if (ASIC_IS_DCE3(rdev)) {
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/* according to the reg specs, this should DCE3.2 only, but in
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* practice it seems to cover DCE3.0/3.1 as well.
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*/
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if (dig->dig_encoder == 0) {
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WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
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WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
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WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
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} else {
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WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
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WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
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WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
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}
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} else {
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/* according to the reg specs, this should be DCE2.0 and DCE3.0 */
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/* according to the reg specs, this should be DCE2.0 and DCE3.0/3.1 */
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WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
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AUDIO_DTO_MODULE(clock / 10));
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}
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