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Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze

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Pull microblaze arch updates from Michal Simek.

* 'next' of git://git.monstr.eu/linux-2.6-microblaze:
  Revert "microblaze_mmu_v2: Update signal returning address"
  microblaze: Added more support for PCI
  microblaze: Prefer to use pr_XXX instead of printk(KERN_XX)
  microblaze: Fix bug with passing command line
  microblaze: Remove PAGE properties duplication
  microblaze: Remove additional andi which has been already done
  microblaze: Use predefined macro for ESR_DIZ
  microblaze: Support 4k/16k/64k pages
  microblaze: Do not used hardcoded value in exception handler
  microblaze: Added fdt chosen capability for timer
  microblaze: Add support for ioreadXX/iowriteXX_rep
  microblaze: Improve failure handling for GPIO reset
  microblaze: clinkage.h
This commit is contained in:
Linus Torvalds 2012-10-07 21:08:40 +09:00
commit 5cad3598ea
12 changed files with 182 additions and 80 deletions
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7
arch/microblaze/Kconfig
View File

@ -243,14 +243,11 @@ choice
config MICROBLAZE_4K_PAGES
bool "4k page size"
config MICROBLAZE_8K_PAGES
bool "8k page size"
config MICROBLAZE_16K_PAGES
bool "16k page size"
config MICROBLAZE_32K_PAGES
bool "32k page size"
config MICROBLAZE_64K_PAGES
bool "64k page size"
endchoice

1
arch/microblaze/include/asm/clinkage.h
View File

@ -1 +0,0 @@
#include <linux/linkage.h>

94
arch/microblaze/include/asm/io.h
View File

@ -35,6 +35,10 @@ extern resource_size_t isa_mem_base;
#define IO_SPACE_LIMIT (0xFFFFFFFF)
/* the following is needed to support PCI with some drivers */
#define mmiowb()
static inline unsigned char __raw_readb(const volatile void __iomem *addr)
{
return *(volatile unsigned char __force *)addr;
@ -248,4 +252,94 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
#define ioport_map(port, nr) ((void __iomem *)(port))
#define ioport_unmap(addr)
/* from asm-generic/io.h */
#ifndef insb
static inline void insb(unsigned long addr, void *buffer, int count)
{
if (count) {
u8 *buf = buffer;
do {
u8 x = inb(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#ifndef insw
static inline void insw(unsigned long addr, void *buffer, int count)
{
if (count) {
u16 *buf = buffer;
do {
u16 x = inw(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#ifndef insl
static inline void insl(unsigned long addr, void *buffer, int count)
{
if (count) {
u32 *buf = buffer;
do {
u32 x = inl(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#ifndef outsb
static inline void outsb(unsigned long addr, const void *buffer, int count)
{
if (count) {
const u8 *buf = buffer;
do {
outb(*buf++, addr);
} while (--count);
}
}
#endif
#ifndef outsw
static inline void outsw(unsigned long addr, const void *buffer, int count)
{
if (count) {
const u16 *buf = buffer;
do {
outw(*buf++, addr);
} while (--count);
}
}
#endif
#ifndef outsl
static inline void outsl(unsigned long addr, const void *buffer, int count)
{
if (count) {
const u32 *buf = buffer;
do {
outl(*buf++, addr);
} while (--count);
}
}
#endif
#define ioread8_rep(p, dst, count) \
insb((unsigned long) (p), (dst), (count))
#define ioread16_rep(p, dst, count) \
insw((unsigned long) (p), (dst), (count))
#define ioread32_rep(p, dst, count) \
insl((unsigned long) (p), (dst), (count))
#define iowrite8_rep(p, src, count) \
outsb((unsigned long) (p), (src), (count))
#define iowrite16_rep(p, src, count) \
outsw((unsigned long) (p), (src), (count))
#define iowrite32_rep(p, src, count) \
outsl((unsigned long) (p), (src), (count))
#endif /* _ASM_MICROBLAZE_IO_H */

9
arch/microblaze/include/asm/page.h
View File

@ -23,12 +23,10 @@
#ifdef __KERNEL__
/* PAGE_SHIFT determines the page size */
#if defined(CONFIG_MICROBLAZE_32K_PAGES)
#define PAGE_SHIFT 15
#if defined(CONFIG_MICROBLAZE_64K_PAGES)
#define PAGE_SHIFT 16
#elif defined(CONFIG_MICROBLAZE_16K_PAGES)
#define PAGE_SHIFT 14
#elif defined(CONFIG_MICROBLAZE_8K_PAGES)
#define PAGE_SHIFT 13
#else
#define PAGE_SHIFT 12
#endif
@ -37,6 +35,8 @@
#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_KERNEL_BASE_ADDR))
#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
#ifndef __ASSEMBLY__
/* MS be sure that SLAB allocates aligned objects */
@ -71,7 +71,6 @@ extern unsigned int __page_offset;
* The basic type of a PTE - 32 bit physical addressing.
*/
typedef unsigned long pte_basic_t;
#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
#define PTE_FMT "%.8lx"
#endif /* CONFIG_MMU */

2
arch/microblaze/include/asm/pci.h
View File

@ -22,6 +22,8 @@
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm-generic/pci-dma-compat.h>
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x10000000

6
arch/microblaze/include/asm/pgtable.h
View File

@ -234,12 +234,6 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
#ifndef _PAGE_SHARED
#define _PAGE_SHARED 0
#endif
#ifndef _PAGE_HWWRITE
#define _PAGE_HWWRITE 0
#endif
#ifndef _PAGE_HWEXEC
#define _PAGE_HWEXEC 0
#endif
#ifndef _PAGE_EXEC
#define _PAGE_EXEC 0
#endif

14
arch/microblaze/kernel/head.S
View File

@ -109,20 +109,24 @@ no_fdt_arg:
#ifndef CONFIG_CMDLINE_BOOL
/*
* handling command line
* copy command line to __init_end. There is space for storing command line.
* copy command line directly to cmd_line placed in data section.
*/
beqid r5, skip /* Skip if NULL pointer */
or r6, r0, r0 /* incremment */
ori r4, r0, __init_end /* load address of command line */
ori r4, r0, cmd_line /* load address of command line */
tophys(r4,r4) /* convert to phys address */
ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
_copy_command_line:
lbu r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */
sb r2, r4, r6 /* addr[r4+r6]= r2*/
/* r2=r5+r6 - r5 contain pointer to command line */
lbu r2, r5, r6
beqid r2, skip /* Skip if no data */
sb r2, r4, r6 /* addr[r4+r6]= r2*/
addik r6, r6, 1 /* increment counting */
bgtid r3, _copy_command_line /* loop for all entries */
addik r3, r3, -1 /* descrement loop */
addik r3, r3, -1 /* decrement loop */
addik r5, r4, 0 /* add new space for command line */
tovirt(r5,r5)
skip:
#endif /* CONFIG_CMDLINE_BOOL */
#ifdef NOT_COMPILE

61
arch/microblaze/kernel/hw_exception_handler.S
View File

@ -75,6 +75,7 @@
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/signal.h>
#include <asm/registers.h>
#include <asm/asm-offsets.h>
#undef DEBUG
@ -581,7 +582,7 @@ ex_handler_done:
* tried to access a kernel or read-protected page - always
* a SEGV). All other faults here must be stores, so no
* need to check ESR_S as well. */
andi r4, r4, 0x800 /* ESR_Z - zone protection */
andi r4, r4, ESR_DIZ /* ESR_Z - zone protection */
bnei r4, ex2
ori r4, r0, swapper_pg_dir
@ -595,25 +596,25 @@ ex_handler_done:
* tried to access a kernel or read-protected page - always
* a SEGV). All other faults here must be stores, so no
* need to check ESR_S as well. */
andi r4, r4, 0x800 /* ESR_Z */
andi r4, r4, ESR_DIZ /* ESR_Z */
bnei r4, ex2
/* get current task address */
addi r4 ,CURRENT_TASK, TOPHYS(0);
lwi r4, r4, TASK_THREAD+PGDIR
ex4:
tophys(r4,r4)
BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
andi r5, r5, 0xffc
/* Create L1 (pgdir/pmd) address */
BSRLI(r5,r3, PGDIR_SHIFT - 2)
andi r5, r5, PAGE_SIZE - 4
/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
or r4, r4, r5
lwi r4, r4, 0 /* Get L1 entry */
andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
beqi r5, ex2 /* Bail if no table */
tophys(r5,r5)
BSRLI(r6,r3,10) /* Compute PTE address */
andi r6, r6, 0xffc
andi r5, r5, 0xfffff003
BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
andi r6, r6, PAGE_SIZE - 4
or r5, r5, r6
lwi r4, r5, 0 /* Get Linux PTE */
@ -632,7 +633,9 @@ ex_handler_done:
* Many of these bits are software only. Bits we don't set
* here we (properly should) assume have the appropriate value.
*/
andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
/* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
TLB_ZSEL(1) | TLB_ATTR_MASK
ori r4, r4, _PAGE_HWEXEC /* make it executable */
/* find the TLB index that caused the fault. It has to be here*/
@ -701,18 +704,18 @@ ex_handler_done:
lwi r4, r4, TASK_THREAD+PGDIR
ex6:
tophys(r4,r4)
BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
andi r5, r5, 0xffc
/* Create L1 (pgdir/pmd) address */
BSRLI(r5,r3, PGDIR_SHIFT - 2)
andi r5, r5, PAGE_SIZE - 4
/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
or r4, r4, r5
lwi r4, r4, 0 /* Get L1 entry */
andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
beqi r5, ex7 /* Bail if no table */
tophys(r5,r5)
BSRLI(r6,r3,10) /* Compute PTE address */
andi r6, r6, 0xffc
andi r5, r5, 0xfffff003
BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
andi r6, r6, PAGE_SIZE - 4
or r5, r5, r6
lwi r4, r5, 0 /* Get Linux PTE */
@ -731,7 +734,8 @@ ex_handler_done:
* here we (properly should) assume have the appropriate value.
*/
brid finish_tlb_load
andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
TLB_ZSEL(1) | TLB_ATTR_MASK
ex7:
/* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
@ -771,18 +775,18 @@ ex_handler_done:
lwi r4, r4, TASK_THREAD+PGDIR
ex9:
tophys(r4,r4)
BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */
andi r5, r5, 0xffc
/* Create L1 (pgdir/pmd) address */
BSRLI(r5,r3, PGDIR_SHIFT - 2)
andi r5, r5, PAGE_SIZE - 4
/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
or r4, r4, r5
lwi r4, r4, 0 /* Get L1 entry */
andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */
andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
beqi r5, ex10 /* Bail if no table */
tophys(r5,r5)
BSRLI(r6,r3,10) /* Compute PTE address */
andi r6, r6, 0xffc
andi r5, r5, 0xfffff003
BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
andi r6, r6, PAGE_SIZE - 4
or r5, r5, r6
lwi r4, r5, 0 /* Get Linux PTE */
@ -801,7 +805,8 @@ ex_handler_done:
* here we (properly should) assume have the appropriate value.
*/
brid finish_tlb_load
andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */
andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
TLB_ZSEL(1) | TLB_ATTR_MASK
ex10:
/* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
@ -854,8 +859,14 @@ ex_handler_done:
* set of bits. These are size, valid, E, U0, and ensure
* bits 20 and 21 are zero.
*/
andi r3, r3, 0xfffff000
ori r3, r3, 0x0c0
andi r3, r3, PAGE_MASK
#ifdef CONFIG_MICROBLAZE_64K_PAGES
ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K)
#elif CONFIG_MICROBLAZE_16K_PAGES
ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K)
#else
ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
#endif
mts rtlbhi, r3 /* Load TLB HI */
nop

21
arch/microblaze/kernel/reset.c
View File

@ -26,13 +26,14 @@ void of_platform_reset_gpio_probe(void)
"hard-reset-gpios", 0);
if (!gpio_is_valid(handle)) {
printk(KERN_INFO "Skipping unavailable RESET gpio %d (%s)\n",
pr_info("Skipping unavailable RESET gpio %d (%s)\n",
handle, "reset");
return;
}
ret = gpio_request(handle, "reset");
if (ret < 0) {
printk(KERN_INFO "GPIO pin is already allocated\n");
pr_info("GPIO pin is already allocated\n");
return;
}
@ -49,7 +50,7 @@ void of_platform_reset_gpio_probe(void)
/* Setup output direction */
gpio_set_value(handle, 0);
printk(KERN_INFO "RESET: Registered gpio device: %d, current val: %d\n",
pr_info("RESET: Registered gpio device: %d, current val: %d\n",
handle, reset_val);
return;
err:
@ -60,7 +61,10 @@ void of_platform_reset_gpio_probe(void)
static void gpio_system_reset(void)
{
gpio_set_value(handle, 1 - reset_val);
if (gpio_is_valid(handle))
gpio_set_value(handle, 1 - reset_val);
else
pr_notice("Reset GPIO unavailable - halting!\n");
}
#else
#define gpio_system_reset() do {} while (0)
@ -72,30 +76,29 @@ void of_platform_reset_gpio_probe(void)
void machine_restart(char *cmd)
{
printk(KERN_NOTICE "Machine restart...\n");
pr_notice("Machine restart...\n");
gpio_system_reset();
dump_stack();
while (1)
;
}
void machine_shutdown(void)
{
printk(KERN_NOTICE "Machine shutdown...\n");
pr_notice("Machine shutdown...\n");
while (1)
;
}
void machine_halt(void)
{
printk(KERN_NOTICE "Machine halt...\n");
pr_notice("Machine halt...\n");
while (1)
;
}
void machine_power_off(void)
{
printk(KERN_NOTICE "Machine power off...\n");
pr_notice("Machine power off...\n");
while (1)
;
}

15
arch/microblaze/kernel/setup.c
View File

@ -40,7 +40,12 @@ DEFINE_PER_CPU(unsigned int, R11_SAVE); /* Temp variable for entry */
DEFINE_PER_CPU(unsigned int, CURRENT_SAVE); /* Saved current pointer */
unsigned int boot_cpuid;
char cmd_line[COMMAND_LINE_SIZE];
/*
* Placed cmd_line to .data section because can be initialized from
* ASM code. Default position is BSS section which is cleared
* in machine_early_init().
*/
char cmd_line[COMMAND_LINE_SIZE] __attribute__ ((section(".data")));
void __init setup_arch(char **cmdline_p)
{
@ -64,7 +69,7 @@ void __init setup_arch(char **cmdline_p)
xilinx_pci_init();
#if defined(CONFIG_SELFMOD_INTC) || defined(CONFIG_SELFMOD_TIMER)
printk(KERN_NOTICE "Self modified code enable\n");
pr_notice("Self modified code enable\n");
#endif
#ifdef CONFIG_VT
@ -130,12 +135,6 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
memset(__bss_start, 0, __bss_stop-__bss_start);
memset(_ssbss, 0, _esbss-_ssbss);
/* Copy command line passed from bootloader */
#ifndef CONFIG_CMDLINE_BOOL
if (cmdline && cmdline[0] != '\0')
strlcpy(cmd_line, cmdline, COMMAND_LINE_SIZE);
#endif
lockdep_init();
/* initialize device tree for usage in early_printk */

8
arch/microblaze/kernel/signal.c
View File

@ -290,15 +290,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
case -ERESTARTNOINTR:
do_restart:
/* offset of 4 bytes to re-execute trap (brki) instruction */
#ifndef CONFIG_MMU
regs->pc -= 4;
#else
/* offset of 8 bytes required = 4 for rtbd
offset, plus 4 for size of
"brki r14,8"
instruction. */
regs->pc -= 8;
#endif
break;
}
}

24
arch/microblaze/kernel/timer.c
View File

@ -116,21 +116,21 @@ static void microblaze_timer_set_mode(enum clock_event_mode mode,
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
printk(KERN_INFO "%s: periodic\n", __func__);
pr_info("%s: periodic\n", __func__);
microblaze_timer0_start_periodic(freq_div_hz);
break;
case CLOCK_EVT_MODE_ONESHOT:
printk(KERN_INFO "%s: oneshot\n", __func__);
pr_info("%s: oneshot\n", __func__);
break;
case CLOCK_EVT_MODE_UNUSED:
printk(KERN_INFO "%s: unused\n", __func__);
pr_info("%s: unused\n", __func__);
break;
case CLOCK_EVT_MODE_SHUTDOWN:
printk(KERN_INFO "%s: shutdown\n", __func__);
pr_info("%s: shutdown\n", __func__);
microblaze_timer0_stop();
break;
case CLOCK_EVT_MODE_RESUME:
printk(KERN_INFO "%s: resume\n", __func__);
pr_info("%s: resume\n", __func__);
break;
}
}
@ -257,7 +257,15 @@ void __init time_init(void)
0
};
#endif
timer = of_find_compatible_node(NULL, NULL, "xlnx,xps-timer-1.00.a");
prop = of_get_property(of_chosen, "system-timer", NULL);
if (prop)
timer = of_find_node_by_phandle(be32_to_cpup(prop));
else
pr_info("No chosen timer found, using default\n");
if (!timer)
timer = of_find_compatible_node(NULL, NULL,
"xlnx,xps-timer-1.00.a");
BUG_ON(!timer);
timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
@ -266,14 +274,14 @@ void __init time_init(void)
timer_num = be32_to_cpup(of_get_property(timer,
"xlnx,one-timer-only", NULL));
if (timer_num) {
printk(KERN_EMERG "Please enable two timers in HW\n");
pr_emerg("Please enable two timers in HW\n");
BUG();
}
#ifdef CONFIG_SELFMOD_TIMER
selfmod_function((int *) arr_func, timer_baseaddr);
#endif
printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
pr_info("%s #0 at 0x%08x, irq=%d\n",
timer->name, timer_baseaddr, irq);
/* If there is clock-frequency property than use it */