arm-soc: driver specific changes
* Updates to the ux500 cpufreq code * Moving the u300 DMA controller driver to drivers/dma * Moving versatile express drivers out of arch/arm for sharing with arch/arm64 * Device tree bindings for the OMAP General Purpose Memory Controller There is a simple conflict in drivers/cpufreq/dbx500-cpufreq.c, because the mach/id.h header and the cpu_is_u8500_family() function in it are now gone. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUSaEc2CrR//JCVInAQKROg//V6LrAmewM4ugCLJFOHDsRN5n27QHOnMb 7g1b56OVtwb+Zer9HLAyZyY6MX12JbDTdC53LDWf6CEU8Z3LfdaPNXyDoGwKQMsA cq2qDufcFoVnaAFMO4uxpe/Y/ZuJJTPm+24dviztMp5PIl4gRkgou5w2fRzd7iLk rETnjvDzB1lKrlrTlnEoPemroErX10AhkjGIQ1zkImqlCOUL1Fs+IMui5gUA3I8X S7q+JPMoIjCFUtuG9QV+/PWcY0SnsGJBZiYdh1XGbCiint5Oi/6hawbBtT4L067H HfSsWe+mx8c2B84V0AFOpKcV6v9VYeyxSkmr40yG3laPReGA8CWjjGQj1kIkyY07 1XujeEjbpp4zgaggtv9Jdb7BAPWWopuqMrpGdcuxBWYN7HwiPoseGzJMo3F7D5Ti KBRsBLDoK514oGLZdgh3i/QQZwhFuJRcHdaoqRU0pWNJBKMxAFdfgeKYdNWtB7HA XrtJvANrrIeKin3bbeodlhaHLxlBImarQjqdK85H0nmLs71jNphihDRVe3wNy5Qu OYbVHbf3cIboIQiLYLgiVc4NxypCXzeAB6pCdX/NWee9P2qgDCb0SEI6OcpBftPh di004nMEquomIkoyNSlAZffcxeUrHiFlqSvHWqzuLqLCGRToxaoWUC0ES3qJA321 23zzC9IYF6Y= =R0p0 -----END PGP SIGNATURE----- Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver specific changes from Arnd Bergmann: - Updates to the ux500 cpufreq code - Moving the u300 DMA controller driver to drivers/dma - Moving versatile express drivers out of arch/arm for sharing with arch/arm64 - Device tree bindings for the OMAP General Purpose Memory Controller * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits) ARM: OMAP2+: gpmc: Add device tree documentation for elm handle ARM: OMAP2+: gpmc: add DT bindings for OneNAND ARM: OMAP2+: gpmc-onenand: drop __init annotation mtd: omap-onenand: pass device_node in platform data ARM: OMAP2+: Prevent potential crash if GPMC probe fails ARM: OMAP2+: gpmc: Remove unneeded of_node_put() arm: Move sp810.h to include/linux/amba/ ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs ARM: OMAP: gpmc-nand: drop __init annotation mtd: omap-nand: pass device_node in platform data ARM: OMAP: gpmc: don't create devices from initcall on DT dma: coh901318: cut down on platform data abstraction dma: coh901318: merge header files dma: coh901318: push definitions into driver dma: coh901318: push header down into the DMA subsystem dma: coh901318: skip hard-coded addresses dma: coh901318: remove hardcoded target addresses dma: coh901318: push platform data into driver dma: coh901318: create a proper platform data file ...
This commit is contained in:
Linus Torvalds
commit
5ce7aba976
84
Documentation/devicetree/bindings/bus/ti-gpmc.txt
Normal file
84
Documentation/devicetree/bindings/bus/ti-gpmc.txt
Normal file
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@ -0,0 +1,84 @@
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Device tree bindings for OMAP general purpose memory controllers (GPMC)
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The actual devices are instantiated from the child nodes of a GPMC node.
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Required properties:
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- compatible: Should be set to one of the following:
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ti,omap2420-gpmc (omap2420)
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ti,omap2430-gpmc (omap2430)
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ti,omap3430-gpmc (omap3430 & omap3630)
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ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
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ti,am3352-gpmc (am335x devices)
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- reg: A resource specifier for the register space
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(see the example below)
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- ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
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completed.
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- #address-cells: Must be set to 2 to allow memory address translation
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- #size-cells: Must be set to 1 to allow CS address passing
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- gpmc,num-cs: The maximum number of chip-select lines that controller
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can support.
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- gpmc,num-waitpins: The maximum number of wait pins that controller can
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support.
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- ranges: Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use:
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<cs-number> 0 <physical address of mapping> <size>
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Currently, calculated values derived from the contents
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of the per-CS register GPMC_CONFIG7 (as set up by the
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bootloader) are used for the physical address decoding.
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As this will change in the future, filling correct
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values here is a requirement.
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Timing properties for child nodes. All are optional and default to 0.
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- gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds
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Chip-select signal timings corresponding to GPMC_CONFIG2:
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- gpmc,cs-on: Assertion time
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- gpmc,cs-rd-off: Read deassertion time
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- gpmc,cs-wr-off: Write deassertion time
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ADV signal timings corresponding to GPMC_CONFIG3:
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- gpmc,adv-on: Assertion time
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- gpmc,adv-rd-off: Read deassertion time
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- gpmc,adv-wr-off: Write deassertion time
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WE signals timings corresponding to GPMC_CONFIG4:
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- gpmc,we-on: Assertion time
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- gpmc,we-off: Deassertion time
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OE signals timings corresponding to GPMC_CONFIG4:
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- gpmc,oe-on: Assertion time
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- gpmc,oe-off: Deassertion time
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Access time and cycle time timings corresponding to GPMC_CONFIG5:
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- gpmc,page-burst-access: Multiple access word delay
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- gpmc,access: Start-cycle to first data valid delay
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- gpmc,rd-cycle: Total read cycle time
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- gpmc,wr-cycle: Total write cycle time
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The following are only applicable to OMAP3+ and AM335x:
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- gpmc,wr-access
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- gpmc,wr-data-mux-bus
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Example for an AM33xx board:
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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reg = <0x50000000 0x2000>;
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interrupts = <100>;
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
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/* child nodes go here */
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};
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80
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Normal file
80
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Normal file
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@ -0,0 +1,80 @@
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Device tree bindings for GPMC connected NANDs
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GPMC connected NAND (found on OMAP boards) are represented as child nodes of
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the GPMC controller with a name of "nand".
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All timing relevant properties as well as generic gpmc child properties are
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explained in a separate documents - please refer to
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Documentation/devicetree/bindings/bus/ti-gpmc.txt
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For NAND specific properties such as ECC modes or bus width, please refer to
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Documentation/devicetree/bindings/mtd/nand.txt
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Required properties:
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- reg: The CS line the peripheral is connected to
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Optional properties:
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- nand-bus-width: Set this numeric value to 16 if the hardware
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is wired that way. If not specified, a bus
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width of 8 is assumed.
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- ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
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"sw" Software method (default)
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"hw" Hardware method
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"hw-romcode" gpmc hamming mode method & romcode layout
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"bch4" 4-bit BCH ecc code
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"bch8" 8-bit BCH ecc code
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- elm_id: Specifies elm device node. This is required to support BCH
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error correction using ELM module.
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For inline partiton table parsing (optional):
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- #address-cells: should be set to 1
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- #size-cells: should be set to 1
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Example for an AM33xx board:
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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reg = <0x50000000 0x1000000>;
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interrupts = <100>;
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */
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elm_id = <&elm>;
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nand@0,0 {
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reg = <0 0 0>; /* CS0, offset 0 */
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nand-bus-width = <16>;
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ti,nand-ecc-opt = "bch8";
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gpmc,sync-clk = <0>;
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gpmc,cs-on = <0>;
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gpmc,cs-rd-off = <44>;
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gpmc,cs-wr-off = <44>;
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gpmc,adv-on = <6>;
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gpmc,adv-rd-off = <34>;
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gpmc,adv-wr-off = <44>;
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gpmc,we-off = <40>;
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gpmc,oe-off = <54>;
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gpmc,access = <64>;
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gpmc,rd-cycle = <82>;
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gpmc,wr-cycle = <82>;
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gpmc,wr-access = <40>;
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gpmc,wr-data-mux-bus = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* partitions go here */
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};
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};
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43
Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
Normal file
43
Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
Normal file
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@ -0,0 +1,43 @@
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Device tree bindings for GPMC connected OneNANDs
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GPMC connected OneNAND (found on OMAP boards) are represented as child nodes of
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the GPMC controller with a name of "onenand".
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All timing relevant properties as well as generic gpmc child properties are
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explained in a separate documents - please refer to
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Documentation/devicetree/bindings/bus/ti-gpmc.txt
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Required properties:
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- reg: The CS line the peripheral is connected to
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Optional properties:
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- dma-channel: DMA Channel index
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For inline partiton table parsing (optional):
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- #address-cells: should be set to 1
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- #size-cells: should be set to 1
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Example for an OMAP3430 board:
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gpmc: gpmc@6e000000 {
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compatible = "ti,omap3430-gpmc";
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ti,hwmods = "gpmc";
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reg = <0x6e000000 0x1000000>;
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interrupts = <20>;
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <4>;
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#address-cells = <2>;
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#size-cells = <1>;
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onenand@0 {
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reg = <0 0 0>; /* CS0, offset 0 */
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#address-cells = <1>;
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#size-cells = <1>;
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/* partitions go here */
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};
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};
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@ -89,20 +89,21 @@ static int omap2_nand_gpmc_retime(
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return 0;
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}
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static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
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static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
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{
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/* support only OMAP3 class */
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if (!cpu_is_omap34xx()) {
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if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
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pr_err("BCH ecc is not supported on this CPU\n");
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return 0;
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}
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/*
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* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
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* Other chips may be added if confirmed to work.
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* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
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* and AM33xx derivates. Other chips may be added if confirmed to work.
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*/
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if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
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(!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
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(!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
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(!soc_is_am33xx())) {
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pr_err("BCH 4-bit mode is not supported on this CPU\n");
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return 0;
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}
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@ -110,8 +111,8 @@ static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
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return 1;
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}
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int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
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struct gpmc_timings *gpmc_t)
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int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
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struct gpmc_timings *gpmc_t)
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{
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int err = 0;
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struct device *dev = &gpmc_nand_device.dev;
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|
|
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@ -356,7 +356,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
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return ret;
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}
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void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
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void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
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{
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int err;
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|
|
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@ -25,6 +25,10 @@
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_mtd.h>
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#include <linux/of_device.h>
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#include <linux/mtd/nand.h>
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#include <linux/platform_data/mtd-nand-omap2.h>
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|
@ -34,6 +38,8 @@
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#include "common.h"
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#include "omap_device.h"
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#include "gpmc.h"
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#include "gpmc-nand.h"
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#include "gpmc-onenand.h"
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#define DEVICE_NAME "omap-gpmc"
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|
@ -145,7 +151,8 @@ static unsigned gpmc_irq_start;
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static struct resource gpmc_mem_root;
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static struct resource gpmc_cs_mem[GPMC_CS_NUM];
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static DEFINE_SPINLOCK(gpmc_mem_lock);
|
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static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
|
||||
/* Define chip-selects as reserved by default until probe completes */
|
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static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
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static struct device *gpmc_dev;
|
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static int gpmc_irq;
|
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static resource_size_t phys_base, mem_size;
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|
|
@ -1118,9 +1125,216 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
|
|||
/* TODO: remove, see function definition */
|
||||
gpmc_convert_ps_to_ns(gpmc_t);
|
||||
|
||||
/* Now the GPMC is initialised, unreserve the chip-selects */
|
||||
gpmc_cs_map = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static struct of_device_id gpmc_dt_ids[] = {
|
||||
{ .compatible = "ti,omap2420-gpmc" },
|
||||
{ .compatible = "ti,omap2430-gpmc" },
|
||||
{ .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
|
||||
{ .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
|
||||
{ .compatible = "ti,am3352-gpmc" }, /* am335x devices */
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
|
||||
|
||||
static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
|
||||
struct gpmc_timings *gpmc_t)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
memset(gpmc_t, 0, sizeof(*gpmc_t));
|
||||
|
||||
/* minimum clock period for syncronous mode */
|
||||
if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
|
||||
gpmc_t->sync_clk = val;
|
||||
|
||||
/* chip select timtings */
|
||||
if (!of_property_read_u32(np, "gpmc,cs-on", &val))
|
||||
gpmc_t->cs_on = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
|
||||
gpmc_t->cs_rd_off = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
|
||||
gpmc_t->cs_wr_off = val;
|
||||
|
||||
/* ADV signal timings */
|
||||
if (!of_property_read_u32(np, "gpmc,adv-on", &val))
|
||||
gpmc_t->adv_on = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
|
||||
gpmc_t->adv_rd_off = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
|
||||
gpmc_t->adv_wr_off = val;
|
||||
|
||||
/* WE signal timings */
|
||||
if (!of_property_read_u32(np, "gpmc,we-on", &val))
|
||||
gpmc_t->we_on = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,we-off", &val))
|
||||
gpmc_t->we_off = val;
|
||||
|
||||
/* OE signal timings */
|
||||
if (!of_property_read_u32(np, "gpmc,oe-on", &val))
|
||||
gpmc_t->oe_on = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,oe-off", &val))
|
||||
gpmc_t->oe_off = val;
|
||||
|
||||
/* access and cycle timings */
|
||||
if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
|
||||
gpmc_t->page_burst_access = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,access", &val))
|
||||
gpmc_t->access = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
|
||||
gpmc_t->rd_cycle = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
|
||||
gpmc_t->wr_cycle = val;
|
||||
|
||||
/* only for OMAP3430 */
|
||||
if (!of_property_read_u32(np, "gpmc,wr-access", &val))
|
||||
gpmc_t->wr_access = val;
|
||||
|
||||
if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
|
||||
gpmc_t->wr_data_mux_bus = val;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MTD_NAND
|
||||
|
||||
static const char * const nand_ecc_opts[] = {
|
||||
[OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
|
||||
[OMAP_ECC_HAMMING_CODE_HW] = "hw",
|
||||
[OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
|
||||
[OMAP_ECC_BCH4_CODE_HW] = "bch4",
|
||||
[OMAP_ECC_BCH8_CODE_HW] = "bch8",
|
||||
};
|
||||
|
||||
static int gpmc_probe_nand_child(struct platform_device *pdev,
|
||||
struct device_node *child)
|
||||
{
|
||||
u32 val;
|
||||
const char *s;
|
||||
struct gpmc_timings gpmc_t;
|
||||
struct omap_nand_platform_data *gpmc_nand_data;
|
||||
|
||||
if (of_property_read_u32(child, "reg", &val) < 0) {
|
||||
dev_err(&pdev->dev, "%s has no 'reg' property\n",
|
||||
child->full_name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
|
||||
GFP_KERNEL);
|
||||
if (!gpmc_nand_data)
|
||||
return -ENOMEM;
|
||||
|
||||
gpmc_nand_data->cs = val;
|
||||
gpmc_nand_data->of_node = child;
|
||||
|
||||
if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
|
||||
for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
|
||||
if (!strcasecmp(s, nand_ecc_opts[val])) {
|
||||
gpmc_nand_data->ecc_opt = val;
|
||||
break;
|
||||
}
|
||||
|
||||
val = of_get_nand_bus_width(child);
|
||||
if (val == 16)
|
||||
gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
|
||||
|
||||
gpmc_read_timings_dt(child, &gpmc_t);
|
||||
gpmc_nand_init(gpmc_nand_data, &gpmc_t);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static int gpmc_probe_nand_child(struct platform_device *pdev,
|
||||
struct device_node *child)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTD_ONENAND
|
||||
static int gpmc_probe_onenand_child(struct platform_device *pdev,
|
||||
struct device_node *child)
|
||||
{
|
||||
u32 val;
|
||||
struct omap_onenand_platform_data *gpmc_onenand_data;
|
||||
|
||||
if (of_property_read_u32(child, "reg", &val) < 0) {
|
||||
dev_err(&pdev->dev, "%s has no 'reg' property\n",
|
||||
child->full_name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
|
||||
GFP_KERNEL);
|
||||
if (!gpmc_onenand_data)
|
||||
return -ENOMEM;
|
||||
|
||||
gpmc_onenand_data->cs = val;
|
||||
gpmc_onenand_data->of_node = child;
|
||||
gpmc_onenand_data->dma_channel = -1;
|
||||
|
||||
if (!of_property_read_u32(child, "dma-channel", &val))
|
||||
gpmc_onenand_data->dma_channel = val;
|
||||
|
||||
gpmc_onenand_init(gpmc_onenand_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static int gpmc_probe_onenand_child(struct platform_device *pdev,
|
||||
struct device_node *child)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int gpmc_probe_dt(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct device_node *child;
|
||||
const struct of_device_id *of_id =
|
||||
of_match_device(gpmc_dt_ids, &pdev->dev);
|
||||
|
||||
if (!of_id)
|
||||
return 0;
|
||||
|
||||
for_each_node_by_name(child, "nand") {
|
||||
ret = gpmc_probe_nand_child(pdev, child);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
for_each_node_by_name(child, "onenand") {
|
||||
ret = gpmc_probe_onenand_child(pdev, child);
|
||||
if (ret < 0) {
|
||||
of_node_put(child);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static int gpmc_probe_dt(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int gpmc_probe(struct platform_device *pdev)
|
||||
{
|
||||
int rc;
|
||||
|
|
@ -1172,6 +1386,14 @@ static int gpmc_probe(struct platform_device *pdev)
|
|||
if (IS_ERR_VALUE(gpmc_setup_irq()))
|
||||
dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
|
||||
|
||||
rc = gpmc_probe_dt(pdev);
|
||||
if (rc < 0) {
|
||||
clk_disable_unprepare(gpmc_l3_clk);
|
||||
clk_put(gpmc_l3_clk);
|
||||
dev_err(gpmc_dev, "failed to probe DT parameters\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1189,6 +1411,7 @@ static struct platform_driver gpmc_driver = {
|
|||
.driver = {
|
||||
.name = DEVICE_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(gpmc_dt_ids),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1212,6 +1435,13 @@ static int __init omap_gpmc_init(void)
|
|||
struct platform_device *pdev;
|
||||
char *oh_name = "gpmc";
|
||||
|
||||
/*
|
||||
* if the board boots up with a populated DT, do not
|
||||
* manually add the device from this initcall
|
||||
*/
|
||||
if (of_have_populated_dt())
|
||||
return -ENODEV;
|
||||
|
||||
oh = omap_hwmod_lookup(oh_name);
|
||||
if (!oh) {
|
||||
pr_err("Could not look up %s\n", oh_name);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,60 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* arch/arm/mach-u300/include/mach/dma_channels.h
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2007-2012 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Map file for the U300 dma driver.
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
*/
|
||||
|
||||
#ifndef DMA_CHANNELS_H
|
||||
#define DMA_CHANNELS_H
|
||||
|
||||
#define U300_DMA_MSL_TX_0 0
|
||||
#define U300_DMA_MSL_TX_1 1
|
||||
#define U300_DMA_MSL_TX_2 2
|
||||
#define U300_DMA_MSL_TX_3 3
|
||||
#define U300_DMA_MSL_TX_4 4
|
||||
#define U300_DMA_MSL_TX_5 5
|
||||
#define U300_DMA_MSL_TX_6 6
|
||||
#define U300_DMA_MSL_RX_0 7
|
||||
#define U300_DMA_MSL_RX_1 8
|
||||
#define U300_DMA_MSL_RX_2 9
|
||||
#define U300_DMA_MSL_RX_3 10
|
||||
#define U300_DMA_MSL_RX_4 11
|
||||
#define U300_DMA_MSL_RX_5 12
|
||||
#define U300_DMA_MSL_RX_6 13
|
||||
#define U300_DMA_MMCSD_RX_TX 14
|
||||
#define U300_DMA_MSPRO_TX 15
|
||||
#define U300_DMA_MSPRO_RX 16
|
||||
#define U300_DMA_UART0_TX 17
|
||||
#define U300_DMA_UART0_RX 18
|
||||
#define U300_DMA_APEX_TX 19
|
||||
#define U300_DMA_APEX_RX 20
|
||||
#define U300_DMA_PCM_I2S0_TX 21
|
||||
#define U300_DMA_PCM_I2S0_RX 22
|
||||
#define U300_DMA_PCM_I2S1_TX 23
|
||||
#define U300_DMA_PCM_I2S1_RX 24
|
||||
#define U300_DMA_XGAM_CDI 25
|
||||
#define U300_DMA_XGAM_PDI 26
|
||||
#define U300_DMA_SPI_TX 27
|
||||
#define U300_DMA_SPI_RX 28
|
||||
#define U300_DMA_GENERAL_PURPOSE_0 29
|
||||
#define U300_DMA_GENERAL_PURPOSE_1 30
|
||||
#define U300_DMA_GENERAL_PURPOSE_2 31
|
||||
#define U300_DMA_GENERAL_PURPOSE_3 32
|
||||
#define U300_DMA_GENERAL_PURPOSE_4 33
|
||||
#define U300_DMA_GENERAL_PURPOSE_5 34
|
||||
#define U300_DMA_GENERAL_PURPOSE_6 35
|
||||
#define U300_DMA_GENERAL_PURPOSE_7 36
|
||||
#define U300_DMA_GENERAL_PURPOSE_8 37
|
||||
#define U300_DMA_UART1_TX 38
|
||||
#define U300_DMA_UART1_RX 39
|
||||
|
||||
#define U300_DMA_DEVICE_CHANNELS 32
|
||||
#define U300_DMA_CHANNELS 40
|
||||
|
||||
|
||||
#endif /* DMA_CHANNELS_H */
|
||||
|
|
@ -1,267 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* include/linux/coh901318.h
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2007-2009 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* DMA driver for COH 901 318
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
*/
|
||||
|
||||
#ifndef COH901318_H
|
||||
#define COH901318_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#define MAX_DMA_PACKET_SIZE_SHIFT 11
|
||||
#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
|
||||
|
||||
/**
|
||||
* struct coh901318_lli - linked list item for DMAC
|
||||
* @control: control settings for DMAC
|
||||
* @src_addr: transfer source address
|
||||
* @dst_addr: transfer destination address
|
||||
* @link_addr: physical address to next lli
|
||||
* @virt_link_addr: virtual address of next lli (only used by pool_free)
|
||||
* @phy_this: physical address of current lli (only used by pool_free)
|
||||
*/
|
||||
struct coh901318_lli {
|
||||
u32 control;
|
||||
dma_addr_t src_addr;
|
||||
dma_addr_t dst_addr;
|
||||
dma_addr_t link_addr;
|
||||
|
||||
void *virt_link_addr;
|
||||
dma_addr_t phy_this;
|
||||
};
|
||||
/**
|
||||
* struct coh901318_params - parameters for DMAC configuration
|
||||
* @config: DMA config register
|
||||
* @ctrl_lli_last: DMA control register for the last lli in the list
|
||||
* @ctrl_lli: DMA control register for an lli
|
||||
* @ctrl_lli_chained: DMA control register for a chained lli
|
||||
*/
|
||||
struct coh901318_params {
|
||||
u32 config;
|
||||
u32 ctrl_lli_last;
|
||||
u32 ctrl_lli;
|
||||
u32 ctrl_lli_chained;
|
||||
};
|
||||
/**
|
||||
* struct coh_dma_channel - dma channel base
|
||||
* @name: ascii name of dma channel
|
||||
* @number: channel id number
|
||||
* @desc_nbr_max: number of preallocated descriptors
|
||||
* @priority_high: prio of channel, 0 low otherwise high.
|
||||
* @param: configuration parameters
|
||||
* @dev_addr: physical address of periphal connected to channel
|
||||
*/
|
||||
struct coh_dma_channel {
|
||||
const char name[32];
|
||||
const int number;
|
||||
const int desc_nbr_max;
|
||||
const int priority_high;
|
||||
const struct coh901318_params param;
|
||||
const dma_addr_t dev_addr;
|
||||
};
|
||||
|
||||
/**
|
||||
* dma_access_memory_state_t - register dma for memory access
|
||||
*
|
||||
* @dev: The dma device
|
||||
* @active: 1 means dma intends to access memory
|
||||
* 0 means dma wont access memory
|
||||
*/
|
||||
typedef void (*dma_access_memory_state_t)(struct device *dev,
|
||||
bool active);
|
||||
|
||||
/**
|
||||
* struct powersave - DMA power save structure
|
||||
* @lock: lock protecting data in this struct
|
||||
* @started_channels: bit mask indicating active dma channels
|
||||
*/
|
||||
struct powersave {
|
||||
spinlock_t lock;
|
||||
u64 started_channels;
|
||||
};
|
||||
/**
|
||||
* struct coh901318_platform - platform arch structure
|
||||
* @chans_slave: specifying dma slave channels
|
||||
* @chans_memcpy: specifying dma memcpy channels
|
||||
* @access_memory_state: requesting DMA memory access (on / off)
|
||||
* @chan_conf: dma channel configurations
|
||||
* @max_channels: max number of dma chanenls
|
||||
*/
|
||||
struct coh901318_platform {
|
||||
const int *chans_slave;
|
||||
const int *chans_memcpy;
|
||||
const dma_access_memory_state_t access_memory_state;
|
||||
const struct coh_dma_channel *chan_conf;
|
||||
const int max_channels;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_COH901318
|
||||
/**
|
||||
* coh901318_filter_id() - DMA channel filter function
|
||||
* @chan: dma channel handle
|
||||
* @chan_id: id of dma channel to be filter out
|
||||
*
|
||||
* In dma_request_channel() it specifies what channel id to be requested
|
||||
*/
|
||||
bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
|
||||
#else
|
||||
static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* DMA Controller - this access the static mappings of the coh901318 dma.
|
||||
*
|
||||
*/
|
||||
|
||||
#define COH901318_MOD32_MASK (0x1F)
|
||||
#define COH901318_WORD_MASK (0xFFFFFFFF)
|
||||
/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_INT_STATUS1 (0x0000)
|
||||
#define COH901318_INT_STATUS2 (0x0004)
|
||||
/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_TC_INT_STATUS1 (0x0008)
|
||||
#define COH901318_TC_INT_STATUS2 (0x000C)
|
||||
/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
|
||||
#define COH901318_TC_INT_CLEAR1 (0x0010)
|
||||
#define COH901318_TC_INT_CLEAR2 (0x0014)
|
||||
/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
|
||||
#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
|
||||
/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_BE_INT_STATUS1 (0x0020)
|
||||
#define COH901318_BE_INT_STATUS2 (0x0024)
|
||||
/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
|
||||
#define COH901318_BE_INT_CLEAR1 (0x0028)
|
||||
#define COH901318_BE_INT_CLEAR2 (0x002C)
|
||||
/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
|
||||
#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
|
||||
#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
|
||||
|
||||
/*
|
||||
* CX_CFG - Channel Configuration Registers 32bit (R/W)
|
||||
*/
|
||||
#define COH901318_CX_CFG (0x0100)
|
||||
#define COH901318_CX_CFG_SPACING (0x04)
|
||||
/* Channel enable activates tha dma job */
|
||||
#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
|
||||
#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
|
||||
/* Request Mode */
|
||||
#define COH901318_CX_CFG_RM_MASK (0x00000006)
|
||||
#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
|
||||
#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
|
||||
#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
|
||||
#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
|
||||
#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
|
||||
/* Linked channel request field. RM must == 11 */
|
||||
#define COH901318_CX_CFG_LCRF_SHIFT 3
|
||||
#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
|
||||
#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
|
||||
/* Terminal Counter Interrupt Request Mask */
|
||||
#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
|
||||
#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
|
||||
/* Bus Error interrupt Mask */
|
||||
#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
|
||||
#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
|
||||
|
||||
/*
|
||||
* CX_STAT - Channel Status Registers 32bit (R/-)
|
||||
*/
|
||||
#define COH901318_CX_STAT (0x0200)
|
||||
#define COH901318_CX_STAT_SPACING (0x04)
|
||||
#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
|
||||
#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
|
||||
#define COH901318_CX_STAT_ACTIVE (0x00000002)
|
||||
#define COH901318_CX_STAT_ENABLED (0x00000001)
|
||||
|
||||
/*
|
||||
* CX_CTRL - Channel Control Registers 32bit (R/W)
|
||||
*/
|
||||
#define COH901318_CX_CTRL (0x0400)
|
||||
#define COH901318_CX_CTRL_SPACING (0x10)
|
||||
/* Transfer Count Enable */
|
||||
#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
|
||||
#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
|
||||
/* Transfer Count Value 0 - 4095 */
|
||||
#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
|
||||
/* Burst count */
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
|
||||
#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
|
||||
/* Source bus size */
|
||||
#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
|
||||
#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
|
||||
#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
|
||||
#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
|
||||
/* Source address increment */
|
||||
#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
|
||||
#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
|
||||
/* Destination Bus Size */
|
||||
#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
|
||||
#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
|
||||
#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
|
||||
#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
|
||||
/* Destination address increment */
|
||||
#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
|
||||
#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
|
||||
/* Master Mode (Master2 is only connected to MSL) */
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
|
||||
#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
|
||||
/* Terminal Count flag to PER enable */
|
||||
#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
|
||||
#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
|
||||
/* Terminal Count flags to CPU enable */
|
||||
#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
|
||||
#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
|
||||
/* Hand shake to peripheral */
|
||||
#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
|
||||
#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
|
||||
#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
|
||||
#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
|
||||
/* DMA mode */
|
||||
#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
|
||||
#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
|
||||
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
|
||||
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
|
||||
/* Primary Request Data Destination */
|
||||
#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
|
||||
#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
|
||||
#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
|
||||
|
||||
/*
|
||||
* CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
|
||||
*/
|
||||
#define COH901318_CX_SRC_ADDR (0x0404)
|
||||
#define COH901318_CX_SRC_ADDR_SPACING (0x10)
|
||||
|
||||
/*
|
||||
* CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
|
||||
*/
|
||||
#define COH901318_CX_DST_ADDR (0x0408)
|
||||
#define COH901318_CX_DST_ADDR_SPACING (0x10)
|
||||
|
||||
/*
|
||||
* CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
|
||||
*/
|
||||
#define COH901318_CX_LNK_ADDR (0x040C)
|
||||
#define COH901318_CX_LNK_ADDR_SPACING (0x10)
|
||||
#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
|
||||
#endif /* COH901318_H */
|
||||
|
|
@ -10,9 +10,8 @@
|
|||
#include <linux/amba/bus.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/platform_data/dma-coh901318.h>
|
||||
#include <linux/err.h>
|
||||
#include <mach/coh901318.h>
|
||||
#include "dma_channels.h"
|
||||
|
||||
/*
|
||||
* The following is for the actual devices on the SSP/SPI bus
|
||||
|
|
|
|||
|
|
@ -11,8 +11,8 @@
|
|||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <linux/io.h>
|
||||
#include <linux/amba/sp810.h>
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/hardware/sp810.h>
|
||||
#include <mach/spear.h>
|
||||
#include <mach/generic.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
* Copyright (C) 2012 ARM Limited
|
||||
*/
|
||||
|
||||
#include <linux/amba/sp810.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
|
|
@ -18,8 +19,6 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/vexpress.h>
|
||||
|
||||
#include <asm/hardware/sp810.h>
|
||||
|
||||
static struct clk *vexpress_sp810_timerclken[4];
|
||||
static DEFINE_SPINLOCK(vexpress_sp810_lock);
|
||||
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/clocksource.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/platform_data/clocksource-nomadik-mtu.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
|
@ -64,6 +65,7 @@ static void __iomem *mtu_base;
|
|||
static bool clkevt_periodic;
|
||||
static u32 clk_prescale;
|
||||
static u32 nmdk_cycle; /* write-once */
|
||||
static struct delay_timer mtu_delay_timer;
|
||||
|
||||
#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
|
||||
/*
|
||||
|
|
@ -80,6 +82,11 @@ static u32 notrace nomadik_read_sched_clock(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
static unsigned long nmdk_timer_read_current_timer(void)
|
||||
{
|
||||
return ~readl_relaxed(mtu_base + MTU_VAL(0));
|
||||
}
|
||||
|
||||
/* Clockevent device: use one-shot mode */
|
||||
static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
|
||||
{
|
||||
|
|
@ -234,4 +241,8 @@ void __init nmdk_timer_init(void __iomem *base, int irq)
|
|||
setup_irq(irq, &nmdk_timer_irq);
|
||||
nmdk_clkevt.cpumask = cpumask_of(0);
|
||||
clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
|
||||
|
||||
mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
|
||||
mtu_delay_timer.freq = rate;
|
||||
register_current_timer_delay(&mtu_delay_timer);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ obj-$(CONFIG_X86_INTEL_PSTATE) += intel_pstate.o
|
|||
|
||||
##################################################################################
|
||||
# ARM SoC drivers
|
||||
obj-$(CONFIG_UX500_SOC_DB8500) += db8500-cpufreq.o
|
||||
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
|
||||
obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
|
||||
obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o
|
||||
obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
/*
|
||||
* Copyright (C) STMicroelectronics 2009
|
||||
* Copyright (C) ST-Ericsson SA 2010
|
||||
* Copyright (C) ST-Ericsson SA 2010-2012
|
||||
*
|
||||
* License Terms: GNU General Public License v2
|
||||
* Author: Sundar Iyer <sundar.iyer@stericsson.com>
|
||||
* Author: Martin Persson <martin.persson@stericsson.com>
|
||||
* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/cpufreq.h>
|
||||
|
|
@ -19,22 +19,23 @@
|
|||
static struct cpufreq_frequency_table *freq_table;
|
||||
static struct clk *armss_clk;
|
||||
|
||||
static struct freq_attr *db8500_cpufreq_attr[] = {
|
||||
static struct freq_attr *dbx500_cpufreq_attr[] = {
|
||||
&cpufreq_freq_attr_scaling_available_freqs,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static int db8500_cpufreq_verify_speed(struct cpufreq_policy *policy)
|
||||
static int dbx500_cpufreq_verify_speed(struct cpufreq_policy *policy)
|
||||
{
|
||||
return cpufreq_frequency_table_verify(policy, freq_table);
|
||||
}
|
||||
|
||||
static int db8500_cpufreq_target(struct cpufreq_policy *policy,
|
||||
static int dbx500_cpufreq_target(struct cpufreq_policy *policy,
|
||||
unsigned int target_freq,
|
||||
unsigned int relation)
|
||||
{
|
||||
struct cpufreq_freqs freqs;
|
||||
unsigned int idx;
|
||||
int ret;
|
||||
|
||||
/* scale the target frequency to one of the extremes supported */
|
||||
if (target_freq < policy->cpuinfo.min_freq)
|
||||
|
|
@ -43,10 +44,9 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy,
|
|||
target_freq = policy->cpuinfo.max_freq;
|
||||
|
||||
/* Lookup the next frequency */
|
||||
if (cpufreq_frequency_table_target
|
||||
(policy, freq_table, target_freq, relation, &idx)) {
|
||||
if (cpufreq_frequency_table_target(policy, freq_table, target_freq,
|
||||
relation, &idx))
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
freqs.old = policy->cur;
|
||||
freqs.new = freq_table[idx].frequency;
|
||||
|
|
@ -59,9 +59,12 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy,
|
|||
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||
|
||||
/* update armss clk frequency */
|
||||
if (clk_set_rate(armss_clk, freq_table[idx].frequency * 1000)) {
|
||||
pr_err("db8500-cpufreq: Failed to update armss clk\n");
|
||||
return -EINVAL;
|
||||
ret = clk_set_rate(armss_clk, freqs.new * 1000);
|
||||
|
||||
if (ret) {
|
||||
pr_err("dbx500-cpufreq: Failed to set armss_clk to %d Hz: error %d\n",
|
||||
freqs.new * 1000, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* post change notification */
|
||||
|
|
@ -71,7 +74,7 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int db8500_cpufreq_getspeed(unsigned int cpu)
|
||||
static unsigned int dbx500_cpufreq_getspeed(unsigned int cpu)
|
||||
{
|
||||
int i = 0;
|
||||
unsigned long freq = clk_get_rate(armss_clk) / 1000;
|
||||
|
|
@ -83,40 +86,26 @@ static unsigned int db8500_cpufreq_getspeed(unsigned int cpu)
|
|||
}
|
||||
|
||||
/* We could not find a corresponding frequency. */
|
||||
pr_err("db8500-cpufreq: Failed to find cpufreq speed\n");
|
||||
pr_err("dbx500-cpufreq: Failed to find cpufreq speed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy)
|
||||
static int __cpuinit dbx500_cpufreq_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
int i = 0;
|
||||
int res;
|
||||
|
||||
armss_clk = clk_get(NULL, "armss");
|
||||
if (IS_ERR(armss_clk)) {
|
||||
pr_err("db8500-cpufreq : Failed to get armss clk\n");
|
||||
return PTR_ERR(armss_clk);
|
||||
}
|
||||
|
||||
pr_info("db8500-cpufreq : Available frequencies:\n");
|
||||
while (freq_table[i].frequency != CPUFREQ_TABLE_END) {
|
||||
pr_info(" %d Mhz\n", freq_table[i].frequency/1000);
|
||||
i++;
|
||||
}
|
||||
|
||||
/* get policy fields based on the table */
|
||||
res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
|
||||
if (!res)
|
||||
cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
|
||||
else {
|
||||
pr_err("db8500-cpufreq : Failed to read policy table\n");
|
||||
clk_put(armss_clk);
|
||||
pr_err("dbx500-cpufreq: Failed to read policy table\n");
|
||||
return res;
|
||||
}
|
||||
|
||||
policy->min = policy->cpuinfo.min_freq;
|
||||
policy->max = policy->cpuinfo.max_freq;
|
||||
policy->cur = db8500_cpufreq_getspeed(policy->cpu);
|
||||
policy->cur = dbx500_cpufreq_getspeed(policy->cpu);
|
||||
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
|
||||
|
||||
/*
|
||||
|
|
@ -132,42 +121,54 @@ static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct cpufreq_driver db8500_cpufreq_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = db8500_cpufreq_verify_speed,
|
||||
.target = db8500_cpufreq_target,
|
||||
.get = db8500_cpufreq_getspeed,
|
||||
.init = db8500_cpufreq_init,
|
||||
.name = "DB8500",
|
||||
.attr = db8500_cpufreq_attr,
|
||||
static struct cpufreq_driver dbx500_cpufreq_driver = {
|
||||
.flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS,
|
||||
.verify = dbx500_cpufreq_verify_speed,
|
||||
.target = dbx500_cpufreq_target,
|
||||
.get = dbx500_cpufreq_getspeed,
|
||||
.init = dbx500_cpufreq_init,
|
||||
.name = "DBX500",
|
||||
.attr = dbx500_cpufreq_attr,
|
||||
};
|
||||
|
||||
static int db8500_cpufreq_probe(struct platform_device *pdev)
|
||||
static int dbx500_cpufreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
freq_table = dev_get_platdata(&pdev->dev);
|
||||
int i = 0;
|
||||
|
||||
freq_table = dev_get_platdata(&pdev->dev);
|
||||
if (!freq_table) {
|
||||
pr_err("db8500-cpufreq: Failed to fetch cpufreq table\n");
|
||||
pr_err("dbx500-cpufreq: Failed to fetch cpufreq table\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return cpufreq_register_driver(&db8500_cpufreq_driver);
|
||||
armss_clk = clk_get(&pdev->dev, "armss");
|
||||
if (IS_ERR(armss_clk)) {
|
||||
pr_err("dbx500-cpufreq: Failed to get armss clk\n");
|
||||
return PTR_ERR(armss_clk);
|
||||
}
|
||||
|
||||
pr_info("dbx500-cpufreq: Available frequencies:\n");
|
||||
while (freq_table[i].frequency != CPUFREQ_TABLE_END) {
|
||||
pr_info(" %d Mhz\n", freq_table[i].frequency/1000);
|
||||
i++;
|
||||
}
|
||||
|
||||
return cpufreq_register_driver(&dbx500_cpufreq_driver);
|
||||
}
|
||||
|
||||
static struct platform_driver db8500_cpufreq_plat_driver = {
|
||||
static struct platform_driver dbx500_cpufreq_plat_driver = {
|
||||
.driver = {
|
||||
.name = "cpufreq-u8500",
|
||||
.name = "cpufreq-ux500",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = db8500_cpufreq_probe,
|
||||
.probe = dbx500_cpufreq_probe,
|
||||
};
|
||||
|
||||
static int __init db8500_cpufreq_register(void)
|
||||
static int __init dbx500_cpufreq_register(void)
|
||||
{
|
||||
pr_info("cpufreq for DB8500 started\n");
|
||||
return platform_driver_register(&db8500_cpufreq_plat_driver);
|
||||
return platform_driver_register(&dbx500_cpufreq_plat_driver);
|
||||
}
|
||||
device_initcall(db8500_cpufreq_register);
|
||||
device_initcall(dbx500_cpufreq_register);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("cpufreq driver for DB8500");
|
||||
MODULE_DESCRIPTION("cpufreq driver for DBX500");
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,16 +1,15 @@
|
|||
/*
|
||||
* driver/dma/coh901318_lli.h
|
||||
*
|
||||
* Copyright (C) 2007-2009 ST-Ericsson
|
||||
* Copyright (C) 2007-2013 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Support functions for handling lli for coh901318
|
||||
* DMA driver for COH 901 318
|
||||
* Author: Per Friden <per.friden@stericsson.com>
|
||||
*/
|
||||
|
||||
#ifndef COH901318_LLI_H
|
||||
#define COH901318_LLI_H
|
||||
#ifndef COH901318_H
|
||||
#define COH901318_H
|
||||
|
||||
#include <mach/coh901318.h>
|
||||
#define MAX_DMA_PACKET_SIZE_SHIFT 11
|
||||
#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
|
||||
|
||||
struct device;
|
||||
|
||||
|
|
@ -24,7 +23,25 @@ struct coh901318_pool {
|
|||
#endif
|
||||
};
|
||||
|
||||
struct device;
|
||||
/**
|
||||
* struct coh901318_lli - linked list item for DMAC
|
||||
* @control: control settings for DMAC
|
||||
* @src_addr: transfer source address
|
||||
* @dst_addr: transfer destination address
|
||||
* @link_addr: physical address to next lli
|
||||
* @virt_link_addr: virtual address of next lli (only used by pool_free)
|
||||
* @phy_this: physical address of current lli (only used by pool_free)
|
||||
*/
|
||||
struct coh901318_lli {
|
||||
u32 control;
|
||||
dma_addr_t src_addr;
|
||||
dma_addr_t dst_addr;
|
||||
dma_addr_t link_addr;
|
||||
|
||||
void *virt_link_addr;
|
||||
dma_addr_t phy_this;
|
||||
};
|
||||
|
||||
/**
|
||||
* coh901318_pool_create() - Creates an dma pool for lli:s
|
||||
* @pool: pool handle
|
||||
|
|
@ -121,4 +138,4 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
|
|||
u32 ctrl, u32 ctrl_last,
|
||||
enum dma_transfer_direction dir, u32 ctrl_irq_mask);
|
||||
|
||||
#endif /* COH901318_LLI_H */
|
||||
#endif /* COH901318_H */
|
||||
|
|
@ -11,9 +11,9 @@
|
|||
#include <linux/memory.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <mach/coh901318.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#include "coh901318_lli.h"
|
||||
#include "coh901318.h"
|
||||
|
||||
#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
|
||||
#define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
|
||||
|
|
|
|||
|
|
@ -3102,8 +3102,8 @@ static struct mfd_cell db8500_prcmu_devs[] = {
|
|||
.pdata_size = sizeof(db8500_regulators),
|
||||
},
|
||||
{
|
||||
.name = "cpufreq-u8500",
|
||||
.of_compatible = "stericsson,cpufreq-u8500",
|
||||
.name = "cpufreq-ux500",
|
||||
.of_compatible = "stericsson,cpufreq-ux500",
|
||||
.platform_data = &db8500_cpufreq_table,
|
||||
.pdata_size = sizeof(db8500_cpufreq_table),
|
||||
},
|
||||
|
|
|
|||
|
|
@ -1332,6 +1332,7 @@ static int omap_nand_probe(struct platform_device *pdev)
|
|||
dma_cap_mask_t mask;
|
||||
unsigned sig;
|
||||
struct resource *res;
|
||||
struct mtd_part_parser_data ppdata = {};
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (pdata == NULL) {
|
||||
|
|
@ -1557,7 +1558,8 @@ static int omap_nand_probe(struct platform_device *pdev)
|
|||
goto out_release_mem_region;
|
||||
}
|
||||
|
||||
mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
|
||||
ppdata.of_node = pdata->of_node;
|
||||
mtd_device_parse_register(&info->mtd, NULL, &ppdata, pdata->parts,
|
||||
pdata->nr_parts);
|
||||
|
||||
platform_set_drvdata(pdev, &info->mtd);
|
||||
|
|
|
|||
|
|
@ -637,6 +637,7 @@ static int omap2_onenand_probe(struct platform_device *pdev)
|
|||
struct onenand_chip *this;
|
||||
int r;
|
||||
struct resource *res;
|
||||
struct mtd_part_parser_data ppdata = {};
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (pdata == NULL) {
|
||||
|
|
@ -767,7 +768,8 @@ static int omap2_onenand_probe(struct platform_device *pdev)
|
|||
if ((r = onenand_scan(&c->mtd, 1)) < 0)
|
||||
goto err_release_regulator;
|
||||
|
||||
r = mtd_device_parse_register(&c->mtd, NULL, NULL,
|
||||
ppdata.of_node = pdata->of_node;
|
||||
r = mtd_device_parse_register(&c->mtd, NULL, &ppdata,
|
||||
pdata ? pdata->parts : NULL,
|
||||
pdata ? pdata->nr_parts : 0);
|
||||
if (r)
|
||||
|
|
|
|||
72
include/linux/platform_data/dma-coh901318.h
Normal file
72
include/linux/platform_data/dma-coh901318.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Platform data for the COH901318 DMA controller
|
||||
* Copyright (C) 2007-2013 ST-Ericsson
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*/
|
||||
|
||||
#ifndef PLAT_COH901318_H
|
||||
#define PLAT_COH901318_H
|
||||
|
||||
#ifdef CONFIG_COH901318
|
||||
|
||||
/* We only support the U300 DMA channels */
|
||||
#define U300_DMA_MSL_TX_0 0
|
||||
#define U300_DMA_MSL_TX_1 1
|
||||
#define U300_DMA_MSL_TX_2 2
|
||||
#define U300_DMA_MSL_TX_3 3
|
||||
#define U300_DMA_MSL_TX_4 4
|
||||
#define U300_DMA_MSL_TX_5 5
|
||||
#define U300_DMA_MSL_TX_6 6
|
||||
#define U300_DMA_MSL_RX_0 7
|
||||
#define U300_DMA_MSL_RX_1 8
|
||||
#define U300_DMA_MSL_RX_2 9
|
||||
#define U300_DMA_MSL_RX_3 10
|
||||
#define U300_DMA_MSL_RX_4 11
|
||||
#define U300_DMA_MSL_RX_5 12
|
||||
#define U300_DMA_MSL_RX_6 13
|
||||
#define U300_DMA_MMCSD_RX_TX 14
|
||||
#define U300_DMA_MSPRO_TX 15
|
||||
#define U300_DMA_MSPRO_RX 16
|
||||
#define U300_DMA_UART0_TX 17
|
||||
#define U300_DMA_UART0_RX 18
|
||||
#define U300_DMA_APEX_TX 19
|
||||
#define U300_DMA_APEX_RX 20
|
||||
#define U300_DMA_PCM_I2S0_TX 21
|
||||
#define U300_DMA_PCM_I2S0_RX 22
|
||||
#define U300_DMA_PCM_I2S1_TX 23
|
||||
#define U300_DMA_PCM_I2S1_RX 24
|
||||
#define U300_DMA_XGAM_CDI 25
|
||||
#define U300_DMA_XGAM_PDI 26
|
||||
#define U300_DMA_SPI_TX 27
|
||||
#define U300_DMA_SPI_RX 28
|
||||
#define U300_DMA_GENERAL_PURPOSE_0 29
|
||||
#define U300_DMA_GENERAL_PURPOSE_1 30
|
||||
#define U300_DMA_GENERAL_PURPOSE_2 31
|
||||
#define U300_DMA_GENERAL_PURPOSE_3 32
|
||||
#define U300_DMA_GENERAL_PURPOSE_4 33
|
||||
#define U300_DMA_GENERAL_PURPOSE_5 34
|
||||
#define U300_DMA_GENERAL_PURPOSE_6 35
|
||||
#define U300_DMA_GENERAL_PURPOSE_7 36
|
||||
#define U300_DMA_GENERAL_PURPOSE_8 37
|
||||
#define U300_DMA_UART1_TX 38
|
||||
#define U300_DMA_UART1_RX 39
|
||||
|
||||
#define U300_DMA_DEVICE_CHANNELS 32
|
||||
#define U300_DMA_CHANNELS 40
|
||||
|
||||
/**
|
||||
* coh901318_filter_id() - DMA channel filter function
|
||||
* @chan: dma channel handle
|
||||
* @chan_id: id of dma channel to be filter out
|
||||
*
|
||||
* In dma_request_channel() it specifies what channel id to be requested
|
||||
*/
|
||||
bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
|
||||
#else
|
||||
static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PLAT_COH901318_H */
|
||||
|
|
@ -60,6 +60,8 @@ struct omap_nand_platform_data {
|
|||
int devsize;
|
||||
enum omap_ecc ecc_opt;
|
||||
struct gpmc_nand_regs reg;
|
||||
};
|
||||
|
||||
/* for passing the partitions */
|
||||
struct device_node *of_node;
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -29,5 +29,8 @@ struct omap_onenand_platform_data {
|
|||
u8 flags;
|
||||
u8 regulator_can_sleep;
|
||||
u8 skip_initial_unlocking;
|
||||
|
||||
/* for passing the partitions */
|
||||
struct device_node *of_node;
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user