rt2x00: Limit txpower by eeprom values
Limit the txpower per rate by the approriate values in the eeprom. This avoids too high txpower values resulting in bad tx performance. Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Helmut Schaa
John W. Linville
parent
8b967e41e0
commit
5e84600491
@ -802,6 +802,18 @@
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*/
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#define EDCA_TID_AC_MAP 0x1310
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/*
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* TX_PWR_CFG:
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*/
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#define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
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#define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
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#define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
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#define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
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#define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
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#define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
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#define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
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#define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
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/*
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* TX_PWR_CFG_0:
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*/
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@ -1853,9 +1865,15 @@ struct mac_iveiv_entry {
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#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
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/*
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* EEPROM TXpower byrate: 20MHZ power
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* EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
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*/
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#define EEPROM_TXPOWER_BYRATE 0x006f
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#define EEPROM_TXPOWER_BYRATE_SIZE 9
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#define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
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#define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
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#define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
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#define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
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/*
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* EEPROM BBP.
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@ -1086,66 +1086,115 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
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}
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static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
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const int txpower)
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const int max_txpower)
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{
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u8 txpower;
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u8 max_value = (u8)max_txpower;
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u16 eeprom;
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int i;
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u32 reg;
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u32 value = TXPOWER_G_TO_DEV(txpower);
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u8 r1;
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u32 offset;
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/*
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* set to normal tx power mode: +/- 0dBm
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*/
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rt2800_bbp_read(rt2x00dev, 1, &r1);
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rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
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rt2800_bbp_write(rt2x00dev, 1, r1);
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rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, ®);
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rt2x00_set_field32(®, TX_PWR_CFG_0_1MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_0_2MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_0_55MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_0_11MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_0_6MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_0_9MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_0_12MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_0_18MBS, value);
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rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
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/*
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* The eeprom contains the tx power values for each rate. These
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* values map to 100% tx power. Each 16bit word contains four tx
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* power values and the order is the same as used in the TX_PWR_CFG
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* registers.
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*/
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offset = TX_PWR_CFG_0;
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rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, ®);
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rt2x00_set_field32(®, TX_PWR_CFG_1_24MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_1_36MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_1_48MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_1_54MBS, value);
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rt2x00_set_field32(®, TX_PWR_CFG_1_MCS0, value);
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rt2x00_set_field32(®, TX_PWR_CFG_1_MCS1, value);
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rt2x00_set_field32(®, TX_PWR_CFG_1_MCS2, value);
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rt2x00_set_field32(®, TX_PWR_CFG_1_MCS3, value);
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rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
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for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
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/* just to be safe */
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if (offset > TX_PWR_CFG_4)
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break;
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rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, ®);
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rt2x00_set_field32(®, TX_PWR_CFG_2_MCS4, value);
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rt2x00_set_field32(®, TX_PWR_CFG_2_MCS5, value);
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rt2x00_set_field32(®, TX_PWR_CFG_2_MCS6, value);
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rt2x00_set_field32(®, TX_PWR_CFG_2_MCS7, value);
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rt2x00_set_field32(®, TX_PWR_CFG_2_MCS8, value);
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rt2x00_set_field32(®, TX_PWR_CFG_2_MCS9, value);
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rt2x00_set_field32(®, TX_PWR_CFG_2_MCS10, value);
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rt2x00_set_field32(®, TX_PWR_CFG_2_MCS11, value);
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rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
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rt2800_register_read(rt2x00dev, offset, ®);
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rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, ®);
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rt2x00_set_field32(®, TX_PWR_CFG_3_MCS12, value);
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rt2x00_set_field32(®, TX_PWR_CFG_3_MCS13, value);
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rt2x00_set_field32(®, TX_PWR_CFG_3_MCS14, value);
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rt2x00_set_field32(®, TX_PWR_CFG_3_MCS15, value);
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rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN1, value);
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rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN2, value);
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rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN3, value);
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rt2x00_set_field32(®, TX_PWR_CFG_3_UKNOWN4, value);
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rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
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/* read the next four txpower values */
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rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
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&eeprom);
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rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, ®);
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rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN5, value);
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rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN6, value);
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rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN7, value);
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rt2x00_set_field32(®, TX_PWR_CFG_4_UKNOWN8, value);
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rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
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/* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
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* TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
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* TX_PWR_CFG_4: unknown */
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE0);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE0,
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min(txpower, max_value));
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/* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
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* TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
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* TX_PWR_CFG_4: unknown */
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE1);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE1,
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min(txpower, max_value));
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/* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
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* TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
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* TX_PWR_CFG_4: unknown */
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE2);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE2,
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min(txpower, max_value));
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/* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
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* TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
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* TX_PWR_CFG_4: unknown */
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE3);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE3,
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min(txpower, max_value));
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/* read the next four txpower values */
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rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
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&eeprom);
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/* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
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* TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
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* TX_PWR_CFG_4: unknown */
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE0);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE4,
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min(txpower, max_value));
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/* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
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* TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
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* TX_PWR_CFG_4: unknown */
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE1);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE5,
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min(txpower, max_value));
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/* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
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* TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
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* TX_PWR_CFG_4: unknown */
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE2);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE6,
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min(txpower, max_value));
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/* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
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* TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
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* TX_PWR_CFG_4: unknown */
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txpower = rt2x00_get_field16(eeprom,
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EEPROM_TXPOWER_BYRATE_RATE3);
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rt2x00_set_field32(®, TX_PWR_CFG_RATE7,
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min(txpower, max_value));
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rt2800_register_write(rt2x00dev, offset, reg);
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/* next TX_PWR_CFG register */
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offset += 4;
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}
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}
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static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
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