pata_efar: fix PIO2 underclocking
Fix the PIO mode 2 using mode 0 timings -- this driver should enable the fast timing bank starting with PIO2, just like the PIIX/ICH drivers do. Also, fix/rephrase some comments while at it. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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@ -22,7 +22,7 @@
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#include <linux/ata.h>
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#include <linux/ata.h>
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#define DRV_NAME "pata_efar"
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#define DRV_NAME "pata_efar"
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#define DRV_VERSION "0.4.4"
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#define DRV_VERSION "0.4.5"
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/**
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/**
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* efar_pre_reset - Enable bits
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* efar_pre_reset - Enable bits
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@ -98,18 +98,17 @@ static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{ 2, 1 },
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{ 2, 1 },
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{ 2, 3 }, };
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{ 2, 3 }, };
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if (pio > 2)
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if (pio > 1)
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control |= 1; /* TIME1 enable */
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control |= 1; /* TIME */
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if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
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if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
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control |= 2; /* IE enable */
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control |= 2; /* IE */
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/* Intel specifies that the PPE functionality is for disk only */
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/* Intel specifies that the prefetch/posting is for disk only */
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if (adev->class == ATA_DEV_ATA)
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if (adev->class == ATA_DEV_ATA)
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control |= 4; /* PPE enable */
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control |= 4; /* PPE */
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pci_read_config_word(dev, idetm_port, &idetm_data);
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pci_read_config_word(dev, idetm_port, &idetm_data);
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/* Enable PPE, IE and TIME as appropriate */
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/* Set PPE, IE, and TIME as appropriate */
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if (adev->devno == 0) {
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if (adev->devno == 0) {
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idetm_data &= 0xCCF0;
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idetm_data &= 0xCCF0;
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idetm_data |= control;
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idetm_data |= control;
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@ -129,7 +128,7 @@ static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
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pci_write_config_byte(dev, 0x44, slave_data);
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pci_write_config_byte(dev, 0x44, slave_data);
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}
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}
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idetm_data |= 0x4000; /* Ensure SITRE is enabled */
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idetm_data |= 0x4000; /* Ensure SITRE is set */
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pci_write_config_word(dev, idetm_port, idetm_data);
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pci_write_config_word(dev, idetm_port, idetm_data);
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}
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}
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