net: dsa: vsc73xx: add support for parallel mode
This patch add platform part of vsc73xx driver. It allows to use chip connected to a parallel memory bus and work in memory-mapped I/O mode. (aka PI bus in chip manual) By default device is working in big endian mode. Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Pawel Dembicki
David S. Miller
parent
95711cd5f0
commit
631e83bf7c
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@ -116,4 +116,13 @@ config NET_DSA_VITESSE_VSC73XX_SPI
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---help---
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This enables support for the Vitesse VSC7385, VSC7388, VSC7395
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and VSC7398 SparX integrated ethernet switches in SPI managed mode.
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config NET_DSA_VITESSE_VSC73XX_PLATFORM
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tristate "Vitesse VSC7385/7388/7395/7398 Platform mode support"
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depends on HAS_IOMEM
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select NET_DSA_VITESSE_VSC73XX
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---help---
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This enables support for the Vitesse VSC7385, VSC7388, VSC7395
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and VSC7398 SparX integrated ethernet switches, connected over
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a CPU-attached address bus and work in memory-mapped I/O mode.
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endmenu
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@ -15,6 +15,7 @@ obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
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obj-$(CONFIG_NET_DSA_SMSC_LAN9303_I2C) += lan9303_i2c.o
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obj-$(CONFIG_NET_DSA_SMSC_LAN9303_MDIO) += lan9303_mdio.o
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obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX) += vitesse-vsc73xx-core.o
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obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM) += vitesse-vsc73xx-platform.o
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obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_SPI) += vitesse-vsc73xx-spi.o
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obj-y += b53/
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obj-y += microchip/
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164
drivers/net/dsa/vitesse-vsc73xx-platform.c
Normal file
164
drivers/net/dsa/vitesse-vsc73xx-platform.c
Normal file
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@ -0,0 +1,164 @@
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// SPDX-License-Identifier: GPL-2.0
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/* DSA driver for:
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* Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
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* Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
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* Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
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* Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
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*
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* This driver takes control of the switch chip connected over CPU-attached
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* address bus and configures it to route packages around when connected to
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* a CPU port.
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*
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* Copyright (C) 2019 Pawel Dembicki <paweldembicki@gmail.com>
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* Based on vitesse-vsc-spi.c by:
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* Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org>
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* Includes portions of code from the firmware uploader by:
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "vitesse-vsc73xx.h"
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#define VSC73XX_CMD_PLATFORM_BLOCK_SHIFT 14
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#define VSC73XX_CMD_PLATFORM_BLOCK_MASK 0x7
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#define VSC73XX_CMD_PLATFORM_SUBBLOCK_SHIFT 10
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#define VSC73XX_CMD_PLATFORM_SUBBLOCK_MASK 0xf
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#define VSC73XX_CMD_PLATFORM_REGISTER_SHIFT 2
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/**
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* struct vsc73xx_platform - VSC73xx Platform state container
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*/
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struct vsc73xx_platform {
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struct platform_device *pdev;
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void __iomem *base_addr;
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struct vsc73xx vsc;
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};
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static const struct vsc73xx_ops vsc73xx_platform_ops;
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static u32 vsc73xx_make_addr(u8 block, u8 subblock, u8 reg)
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{
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u32 ret;
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ret = (block & VSC73XX_CMD_PLATFORM_BLOCK_MASK)
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<< VSC73XX_CMD_PLATFORM_BLOCK_SHIFT;
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ret |= (subblock & VSC73XX_CMD_PLATFORM_SUBBLOCK_MASK)
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<< VSC73XX_CMD_PLATFORM_SUBBLOCK_SHIFT;
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ret |= reg << VSC73XX_CMD_PLATFORM_REGISTER_SHIFT;
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return ret;
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}
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static int vsc73xx_platform_read(struct vsc73xx *vsc, u8 block, u8 subblock,
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u8 reg, u32 *val)
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{
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struct vsc73xx_platform *vsc_platform = vsc->priv;
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u32 offset;
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if (!vsc73xx_is_addr_valid(block, subblock))
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return -EINVAL;
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offset = vsc73xx_make_addr(block, subblock, reg);
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/* By default vsc73xx running in big-endian mode.
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* (See "Register Addressing" section 5.5.3 in the VSC7385 manual.)
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*/
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*val = ioread32be(vsc_platform->base_addr + offset);
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return 0;
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}
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static int vsc73xx_platform_write(struct vsc73xx *vsc, u8 block, u8 subblock,
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u8 reg, u32 val)
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{
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struct vsc73xx_platform *vsc_platform = vsc->priv;
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u32 offset;
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if (!vsc73xx_is_addr_valid(block, subblock))
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return -EINVAL;
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offset = vsc73xx_make_addr(block, subblock, reg);
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iowrite32be(val, vsc_platform->base_addr + offset);
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return 0;
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}
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static int vsc73xx_platform_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct vsc73xx_platform *vsc_platform;
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struct resource *res = NULL;
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int ret;
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vsc_platform = devm_kzalloc(dev, sizeof(*vsc_platform), GFP_KERNEL);
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if (!vsc_platform)
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return -ENOMEM;
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platform_set_drvdata(pdev, vsc_platform);
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vsc_platform->pdev = pdev;
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vsc_platform->vsc.dev = dev;
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vsc_platform->vsc.priv = vsc_platform;
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vsc_platform->vsc.ops = &vsc73xx_platform_ops;
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/* obtain I/O memory space */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
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ret = -ENXIO;
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return ret;
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}
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vsc_platform->base_addr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(vsc_platform->base_addr)) {
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dev_err(&pdev->dev, "cannot request I/O memory space\n");
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ret = -ENXIO;
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return ret;
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}
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return vsc73xx_probe(&vsc_platform->vsc);
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}
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static int vsc73xx_platform_remove(struct platform_device *pdev)
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{
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struct vsc73xx_platform *vsc_platform = platform_get_drvdata(pdev);
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return vsc73xx_remove(&vsc_platform->vsc);
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}
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static const struct vsc73xx_ops vsc73xx_platform_ops = {
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.read = vsc73xx_platform_read,
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.write = vsc73xx_platform_write,
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};
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static const struct of_device_id vsc73xx_of_match[] = {
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{
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.compatible = "vitesse,vsc7385",
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},
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{
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.compatible = "vitesse,vsc7388",
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},
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{
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.compatible = "vitesse,vsc7395",
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},
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{
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.compatible = "vitesse,vsc7398",
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, vsc73xx_of_match);
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static struct platform_driver vsc73xx_platform_driver = {
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.probe = vsc73xx_platform_probe,
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.remove = vsc73xx_platform_remove,
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.driver = {
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.name = "vsc73xx-platform",
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.of_match_table = vsc73xx_of_match,
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},
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};
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module_platform_driver(vsc73xx_platform_driver);
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MODULE_AUTHOR("Pawel Dembicki <paweldembicki@gmail.com>");
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MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 Platform driver");
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MODULE_LICENSE("GPL v2");
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