spi: octeon: Split driver into Octeon specific and common parts
Separate driver probing from SPI transfer functions. Signed-off-by: Jan Glauber <jglauber@cavium.com> Tested-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jan Glauber
Mark Brown
parent
22cc1b6b35
commit
63d49afefc
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@ -56,6 +56,7 @@ obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
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obj-$(CONFIG_SPI_MXS) += spi-mxs.o
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obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
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obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
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spi-octeon-objs := spi-cavium.o spi-cavium-octeon.o
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obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
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obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
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obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
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104
drivers/spi/spi-cavium-octeon.c
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104
drivers/spi/spi-cavium-octeon.c
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@ -0,0 +1,104 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011, 2012 Cavium, Inc.
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*/
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <asm/octeon/octeon.h>
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#include "spi-cavium.h"
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static int octeon_spi_probe(struct platform_device *pdev)
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{
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struct resource *res_mem;
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void __iomem *reg_base;
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struct spi_master *master;
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struct octeon_spi *p;
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int err = -ENOENT;
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master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
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if (!master)
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return -ENOMEM;
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p = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, master);
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res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
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if (IS_ERR(reg_base)) {
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err = PTR_ERR(reg_base);
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goto fail;
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}
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p->register_base = reg_base;
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p->sys_freq = octeon_get_io_clock_rate();
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p->regs.config = 0;
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p->regs.status = 0x08;
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p->regs.tx = 0x10;
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p->regs.data = 0x80;
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master->num_chipselect = 4;
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master->mode_bits = SPI_CPHA |
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SPI_CPOL |
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SPI_CS_HIGH |
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SPI_LSB_FIRST |
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SPI_3WIRE;
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master->transfer_one_message = octeon_spi_transfer_one_message;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
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master->dev.of_node = pdev->dev.of_node;
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err = devm_spi_register_master(&pdev->dev, master);
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if (err) {
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dev_err(&pdev->dev, "register master failed: %d\n", err);
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goto fail;
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}
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dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
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return 0;
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fail:
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spi_master_put(master);
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return err;
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}
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static int octeon_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct octeon_spi *p = spi_master_get_devdata(master);
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/* Clear the CSENA* and put everything in a known state. */
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writeq(0, p->register_base + OCTEON_SPI_CFG(p));
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return 0;
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}
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static const struct of_device_id octeon_spi_match[] = {
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{ .compatible = "cavium,octeon-3010-spi", },
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_spi_match);
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static struct platform_driver octeon_spi_driver = {
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.driver = {
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.name = "spi-octeon",
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.of_match_table = octeon_spi_match,
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},
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.probe = octeon_spi_probe,
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.remove = octeon_spi_remove,
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};
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module_platform_driver(octeon_spi_driver);
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MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
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MODULE_AUTHOR("David Daney");
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MODULE_LICENSE("GPL");
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@ -6,42 +6,13 @@
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* Copyright (C) 2011, 2012 Cavium, Inc.
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*/
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <asm/octeon/octeon.h>
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#include "spi-cavium.h"
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#define OCTEON_SPI_MAX_BYTES 9
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#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
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struct octeon_spi_regs {
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int config;
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int status;
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int tx;
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int data;
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};
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struct octeon_spi {
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void __iomem *register_base;
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u64 last_cfg;
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u64 cs_enax;
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int sys_freq;
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struct octeon_spi_regs regs;
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};
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#define OCTEON_SPI_CFG(x) (x->regs.config)
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#define OCTEON_SPI_STS(x) (x->regs.status)
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#define OCTEON_SPI_TX(x) (x->regs.tx)
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#define OCTEON_SPI_DAT0(x) (x->regs.data)
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static void octeon_spi_wait_ready(struct octeon_spi *p)
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{
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union cvmx_mpi_sts mpi_sts;
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@ -154,8 +125,8 @@ static int octeon_spi_do_transfer(struct octeon_spi *p,
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return xfer->len;
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}
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static int octeon_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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int octeon_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct octeon_spi *p = spi_master_get_devdata(master);
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unsigned int total_len = 0;
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@ -178,90 +149,3 @@ static int octeon_spi_transfer_one_message(struct spi_master *master,
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spi_finalize_current_message(master);
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return status;
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}
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static int octeon_spi_probe(struct platform_device *pdev)
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{
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struct resource *res_mem;
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void __iomem *reg_base;
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struct spi_master *master;
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struct octeon_spi *p;
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int err = -ENOENT;
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master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
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if (!master)
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return -ENOMEM;
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p = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, master);
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res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg_base = devm_ioremap_resource(&pdev->dev, res_mem);
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if (IS_ERR(reg_base)) {
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err = PTR_ERR(reg_base);
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goto fail;
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}
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p->register_base = reg_base;
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p->sys_freq = octeon_get_io_clock_rate();
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p->regs.config = 0;
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p->regs.status = 0x08;
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p->regs.tx = 0x10;
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p->regs.data = 0x80;
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master->num_chipselect = 4;
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master->mode_bits = SPI_CPHA |
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SPI_CPOL |
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SPI_CS_HIGH |
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SPI_LSB_FIRST |
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SPI_3WIRE;
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master->transfer_one_message = octeon_spi_transfer_one_message;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
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master->dev.of_node = pdev->dev.of_node;
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err = devm_spi_register_master(&pdev->dev, master);
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if (err) {
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dev_err(&pdev->dev, "register master failed: %d\n", err);
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goto fail;
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}
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dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
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return 0;
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fail:
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spi_master_put(master);
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return err;
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}
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static int octeon_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct octeon_spi *p = spi_master_get_devdata(master);
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/* Clear the CSENA* and put everything in a known state. */
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writeq(0, p->register_base + OCTEON_SPI_CFG(p));
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return 0;
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}
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static const struct of_device_id octeon_spi_match[] = {
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{ .compatible = "cavium,octeon-3010-spi", },
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_spi_match);
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static struct platform_driver octeon_spi_driver = {
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.driver = {
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.name = "spi-octeon",
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.of_match_table = octeon_spi_match,
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},
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.probe = octeon_spi_probe,
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.remove = octeon_spi_remove,
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};
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module_platform_driver(octeon_spi_driver);
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MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
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MODULE_AUTHOR("David Daney");
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MODULE_LICENSE("GPL");
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@ -1,3 +1,32 @@
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#ifndef __SPI_CAVIUM_H
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#define __SPI_CAVIUM_H
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#define OCTEON_SPI_MAX_BYTES 9
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#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
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struct octeon_spi_regs {
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int config;
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int status;
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int tx;
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int data;
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};
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struct octeon_spi {
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void __iomem *register_base;
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u64 last_cfg;
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u64 cs_enax;
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int sys_freq;
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struct octeon_spi_regs regs;
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};
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#define OCTEON_SPI_CFG(x) (x->regs.config)
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#define OCTEON_SPI_STS(x) (x->regs.status)
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#define OCTEON_SPI_TX(x) (x->regs.tx)
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#define OCTEON_SPI_DAT0(x) (x->regs.data)
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int octeon_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg);
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/* MPI register descriptions */
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#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
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@ -296,3 +325,5 @@ union cvmx_mpi_tx {
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struct cvmx_mpi_tx_s cn66xx;
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struct cvmx_mpi_tx_cn61xx cnf71xx;
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};
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#endif /* __SPI_CAVIUM_H */
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