Merge branch 'devel-dma' into omap-for-linus
This commit is contained in:
Tony Lindgren
commit
6971071cdd
@ -3,7 +3,7 @@
|
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#
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||||
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# Common support
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obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o
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obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o
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||||
obj-y += clock.o clock_data.o opp_data.o
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||||
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obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
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|
||||
390
arch/arm/mach-omap1/dma.c
Normal file
390
arch/arm/mach-omap1/dma.c
Normal file
@ -0,0 +1,390 @@
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||||
/*
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* OMAP1/OMAP7xx - specific DMA driver
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*
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* Copyright (C) 2003 - 2008 Nokia Corporation
|
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* Author: Juha Yrjölä <juha.yrjola@nokia.com>
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||||
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
|
||||
* Graphics DMA and LCD DMA graphics tranformations
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* by Imre Deak <imre.deak@nokia.com>
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||||
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
|
||||
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
|
||||
*
|
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Converted DMA library into platform driver
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* - G, Manjunath Kondaiah <manjugk@ti.com>
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||||
*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
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|
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#include <linux/err.h>
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#include <linux/io.h>
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||||
#include <linux/slab.h>
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||||
#include <linux/module.h>
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||||
#include <linux/init.h>
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||||
#include <linux/device.h>
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#include <plat/dma.h>
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#include <plat/tc.h>
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#include <plat/irqs.h>
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#define OMAP1_DMA_BASE (0xfffed800)
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#define OMAP1_LOGICAL_DMA_CH_COUNT 17
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#define OMAP1_DMA_STRIDE 0x40
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static u32 errata;
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static u32 enable_1510_mode;
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static u8 dma_stride;
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static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
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static u16 reg_map[] = {
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[GCR] = 0x400,
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[GSCR] = 0x404,
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[GRST1] = 0x408,
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[HW_ID] = 0x442,
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[PCH2_ID] = 0x444,
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[PCH0_ID] = 0x446,
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[PCH1_ID] = 0x448,
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[PCHG_ID] = 0x44a,
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[PCHD_ID] = 0x44c,
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[CAPS_0] = 0x44e,
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[CAPS_1] = 0x452,
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[CAPS_2] = 0x456,
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[CAPS_3] = 0x458,
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[CAPS_4] = 0x45a,
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[PCH2_SR] = 0x460,
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[PCH0_SR] = 0x480,
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[PCH1_SR] = 0x482,
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[PCHD_SR] = 0x4c0,
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/* Common Registers */
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[CSDP] = 0x00,
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[CCR] = 0x02,
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[CICR] = 0x04,
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[CSR] = 0x06,
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[CEN] = 0x10,
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[CFN] = 0x12,
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[CSFI] = 0x14,
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[CSEI] = 0x16,
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[CPC] = 0x18, /* 15xx only */
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[CSAC] = 0x18,
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[CDAC] = 0x1a,
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[CDEI] = 0x1c,
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[CDFI] = 0x1e,
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[CLNK_CTRL] = 0x28,
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/* Channel specific register offsets */
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[CSSA] = 0x08,
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[CDSA] = 0x0c,
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[COLOR] = 0x20,
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[CCR2] = 0x24,
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[LCH_CTRL] = 0x2a,
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};
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static struct resource res[] __initdata = {
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[0] = {
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.start = OMAP1_DMA_BASE,
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.end = OMAP1_DMA_BASE + SZ_2K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.name = "0",
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.start = INT_DMA_CH0_6,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.name = "1",
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.start = INT_DMA_CH1_7,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.name = "2",
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.start = INT_DMA_CH2_8,
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.flags = IORESOURCE_IRQ,
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},
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[4] = {
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.name = "3",
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.start = INT_DMA_CH3,
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.flags = IORESOURCE_IRQ,
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},
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[5] = {
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.name = "4",
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.start = INT_DMA_CH4,
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.flags = IORESOURCE_IRQ,
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},
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[6] = {
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.name = "5",
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.start = INT_DMA_CH5,
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.flags = IORESOURCE_IRQ,
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},
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/* Handled in lcd_dma.c */
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[7] = {
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.name = "6",
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.start = INT_1610_DMA_CH6,
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.flags = IORESOURCE_IRQ,
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},
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/* irq's for omap16xx and omap7xx */
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[8] = {
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.name = "7",
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.start = INT_1610_DMA_CH7,
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.flags = IORESOURCE_IRQ,
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},
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[9] = {
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.name = "8",
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.start = INT_1610_DMA_CH8,
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.flags = IORESOURCE_IRQ,
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},
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[10] = {
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.name = "9",
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.start = INT_1610_DMA_CH9,
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.flags = IORESOURCE_IRQ,
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},
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[11] = {
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.name = "10",
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.start = INT_1610_DMA_CH10,
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.flags = IORESOURCE_IRQ,
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},
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[12] = {
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.name = "11",
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.start = INT_1610_DMA_CH11,
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.flags = IORESOURCE_IRQ,
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},
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[13] = {
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.name = "12",
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.start = INT_1610_DMA_CH12,
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.flags = IORESOURCE_IRQ,
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},
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[14] = {
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.name = "13",
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.start = INT_1610_DMA_CH13,
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.flags = IORESOURCE_IRQ,
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},
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[15] = {
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.name = "14",
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.start = INT_1610_DMA_CH14,
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.flags = IORESOURCE_IRQ,
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},
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[16] = {
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.name = "15",
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.start = INT_1610_DMA_CH15,
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.flags = IORESOURCE_IRQ,
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},
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[17] = {
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.name = "16",
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.start = INT_DMA_LCD,
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.flags = IORESOURCE_IRQ,
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},
|
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};
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static void __iomem *dma_base;
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static inline void dma_write(u32 val, int reg, int lch)
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{
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u8 stride;
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u32 offset;
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stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
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offset = reg_map[reg] + (stride * lch);
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__raw_writew(val, dma_base + offset);
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if ((reg > CLNK_CTRL && reg < CCEN) ||
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(reg > PCHD_ID && reg < CAPS_2)) {
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u32 offset2 = reg_map[reg] + 2 + (stride * lch);
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__raw_writew(val >> 16, dma_base + offset2);
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}
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}
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static inline u32 dma_read(int reg, int lch)
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{
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u8 stride;
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u32 offset, val;
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stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
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offset = reg_map[reg] + (stride * lch);
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val = __raw_readw(dma_base + offset);
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if ((reg > CLNK_CTRL && reg < CCEN) ||
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(reg > PCHD_ID && reg < CAPS_2)) {
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u16 upper;
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u32 offset2 = reg_map[reg] + 2 + (stride * lch);
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upper = __raw_readw(dma_base + offset2);
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val |= (upper << 16);
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}
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return val;
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}
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static void omap1_clear_lch_regs(int lch)
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{
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int i = dma_common_ch_start;
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for (; i <= dma_common_ch_end; i += 1)
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dma_write(0, i, lch);
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}
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static void omap1_clear_dma(int lch)
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{
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u32 l;
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l = dma_read(CCR, lch);
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l &= ~OMAP_DMA_CCR_EN;
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dma_write(l, CCR, lch);
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/* Clear pending interrupts */
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l = dma_read(CSR, lch);
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}
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static void omap1_show_dma_caps(void)
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{
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if (enable_1510_mode) {
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printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
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} else {
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u16 w;
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||||
printk(KERN_INFO "OMAP DMA hardware version %d\n",
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||||
dma_read(HW_ID, 0));
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printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
|
||||
dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
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dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
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||||
dma_read(CAPS_4, 0));
|
||||
|
||||
/* Disable OMAP 3.0/3.1 compatibility mode. */
|
||||
w = dma_read(GSCR, 0);
|
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w |= 1 << 3;
|
||||
dma_write(w, GSCR, 0);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static u32 configure_dma_errata(void)
|
||||
{
|
||||
|
||||
/*
|
||||
* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
|
||||
* read before the DMA controller finished disabling the channel.
|
||||
*/
|
||||
if (!cpu_is_omap15xx())
|
||||
SET_DMA_ERRATA(DMA_ERRATA_3_3);
|
||||
|
||||
return errata;
|
||||
}
|
||||
|
||||
static int __init omap1_system_dma_init(void)
|
||||
{
|
||||
struct omap_system_dma_plat_info *p;
|
||||
struct omap_dma_dev_attr *d;
|
||||
struct platform_device *pdev;
|
||||
int ret;
|
||||
|
||||
pdev = platform_device_alloc("omap_dma_system", 0);
|
||||
if (!pdev) {
|
||||
pr_err("%s: Unable to device alloc for dma\n",
|
||||
__func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dma_base = ioremap(res[0].start, resource_size(&res[0]));
|
||||
if (!dma_base) {
|
||||
pr_err("%s: Unable to ioremap\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
|
||||
__func__, pdev->name, pdev->id);
|
||||
goto exit_device_del;
|
||||
}
|
||||
|
||||
p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
|
||||
if (!p) {
|
||||
dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
|
||||
__func__, pdev->name);
|
||||
ret = -ENOMEM;
|
||||
goto exit_device_put;
|
||||
}
|
||||
|
||||
d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
|
||||
if (!d) {
|
||||
dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
|
||||
__func__, pdev->name);
|
||||
ret = -ENOMEM;
|
||||
goto exit_release_p;
|
||||
}
|
||||
|
||||
d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
|
||||
|
||||
/* Valid attributes for omap1 plus processors */
|
||||
if (cpu_is_omap15xx())
|
||||
d->dev_caps = ENABLE_1510_MODE;
|
||||
enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
|
||||
|
||||
d->dev_caps |= SRC_PORT;
|
||||
d->dev_caps |= DST_PORT;
|
||||
d->dev_caps |= SRC_INDEX;
|
||||
d->dev_caps |= DST_INDEX;
|
||||
d->dev_caps |= IS_BURST_ONLY4;
|
||||
d->dev_caps |= CLEAR_CSR_ON_READ;
|
||||
d->dev_caps |= IS_WORD_16;
|
||||
|
||||
|
||||
d->chan = kzalloc(sizeof(struct omap_dma_lch) *
|
||||
(d->lch_count), GFP_KERNEL);
|
||||
if (!d->chan) {
|
||||
dev_err(&pdev->dev, "%s: Memory allocation failed"
|
||||
"for d->chan!!!\n", __func__);
|
||||
goto exit_release_d;
|
||||
}
|
||||
|
||||
if (cpu_is_omap15xx())
|
||||
d->chan_count = 9;
|
||||
else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
|
||||
if (!(d->dev_caps & ENABLE_1510_MODE))
|
||||
d->chan_count = 16;
|
||||
else
|
||||
d->chan_count = 9;
|
||||
}
|
||||
|
||||
p->dma_attr = d;
|
||||
|
||||
p->show_dma_caps = omap1_show_dma_caps;
|
||||
p->clear_lch_regs = omap1_clear_lch_regs;
|
||||
p->clear_dma = omap1_clear_dma;
|
||||
p->dma_write = dma_write;
|
||||
p->dma_read = dma_read;
|
||||
p->disable_irq_lch = NULL;
|
||||
|
||||
p->errata = configure_dma_errata();
|
||||
|
||||
ret = platform_device_add_data(pdev, p, sizeof(*p));
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
|
||||
__func__, pdev->name, pdev->id);
|
||||
goto exit_release_chan;
|
||||
}
|
||||
|
||||
ret = platform_device_add(pdev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
|
||||
__func__, pdev->name, pdev->id);
|
||||
goto exit_release_chan;
|
||||
}
|
||||
|
||||
dma_stride = OMAP1_DMA_STRIDE;
|
||||
dma_common_ch_start = CPC;
|
||||
dma_common_ch_end = COLOR;
|
||||
|
||||
return ret;
|
||||
|
||||
exit_release_chan:
|
||||
kfree(d->chan);
|
||||
exit_release_d:
|
||||
kfree(d);
|
||||
exit_release_p:
|
||||
kfree(p);
|
||||
exit_device_put:
|
||||
platform_device_put(pdev);
|
||||
exit_device_del:
|
||||
platform_device_del(pdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
arch_initcall(omap1_system_dma_init);
|
||||
@ -4,7 +4,7 @@
|
||||
|
||||
# Common support
|
||||
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
|
||||
common.o gpio.o
|
||||
common.o gpio.o dma.o
|
||||
|
||||
omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
|
||||
hwmod-common = omap_hwmod.o \
|
||||
|
||||
297
arch/arm/mach-omap2/dma.c
Normal file
297
arch/arm/mach-omap2/dma.c
Normal file
@ -0,0 +1,297 @@
|
||||
/*
|
||||
* OMAP2+ DMA driver
|
||||
*
|
||||
* Copyright (C) 2003 - 2008 Nokia Corporation
|
||||
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
|
||||
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
|
||||
* Graphics DMA and LCD DMA graphics tranformations
|
||||
* by Imre Deak <imre.deak@nokia.com>
|
||||
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
|
||||
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments
|
||||
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
*
|
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Converted DMA library into platform driver
|
||||
* - G, Manjunath Kondaiah <manjugk@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/omap_device.h>
|
||||
#include <plat/dma.h>
|
||||
|
||||
#define OMAP2_DMA_STRIDE 0x60
|
||||
|
||||
static u32 errata;
|
||||
static u8 dma_stride;
|
||||
|
||||
static struct omap_dma_dev_attr *d;
|
||||
|
||||
static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
|
||||
|
||||
static u16 reg_map[] = {
|
||||
[REVISION] = 0x00,
|
||||
[GCR] = 0x78,
|
||||
[IRQSTATUS_L0] = 0x08,
|
||||
[IRQSTATUS_L1] = 0x0c,
|
||||
[IRQSTATUS_L2] = 0x10,
|
||||
[IRQSTATUS_L3] = 0x14,
|
||||
[IRQENABLE_L0] = 0x18,
|
||||
[IRQENABLE_L1] = 0x1c,
|
||||
[IRQENABLE_L2] = 0x20,
|
||||
[IRQENABLE_L3] = 0x24,
|
||||
[SYSSTATUS] = 0x28,
|
||||
[OCP_SYSCONFIG] = 0x2c,
|
||||
[CAPS_0] = 0x64,
|
||||
[CAPS_2] = 0x6c,
|
||||
[CAPS_3] = 0x70,
|
||||
[CAPS_4] = 0x74,
|
||||
|
||||
/* Common register offsets */
|
||||
[CCR] = 0x80,
|
||||
[CLNK_CTRL] = 0x84,
|
||||
[CICR] = 0x88,
|
||||
[CSR] = 0x8c,
|
||||
[CSDP] = 0x90,
|
||||
[CEN] = 0x94,
|
||||
[CFN] = 0x98,
|
||||
[CSEI] = 0xa4,
|
||||
[CSFI] = 0xa8,
|
||||
[CDEI] = 0xac,
|
||||
[CDFI] = 0xb0,
|
||||
[CSAC] = 0xb4,
|
||||
[CDAC] = 0xb8,
|
||||
|
||||
/* Channel specific register offsets */
|
||||
[CSSA] = 0x9c,
|
||||
[CDSA] = 0xa0,
|
||||
[CCEN] = 0xbc,
|
||||
[CCFN] = 0xc0,
|
||||
[COLOR] = 0xc4,
|
||||
|
||||
/* OMAP4 specific registers */
|
||||
[CDP] = 0xd0,
|
||||
[CNDP] = 0xd4,
|
||||
[CCDN] = 0xd8,
|
||||
};
|
||||
|
||||
static struct omap_device_pm_latency omap2_dma_latency[] = {
|
||||
{
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
static void __iomem *dma_base;
|
||||
static inline void dma_write(u32 val, int reg, int lch)
|
||||
{
|
||||
u8 stride;
|
||||
u32 offset;
|
||||
|
||||
stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
|
||||
offset = reg_map[reg] + (stride * lch);
|
||||
__raw_writel(val, dma_base + offset);
|
||||
}
|
||||
|
||||
static inline u32 dma_read(int reg, int lch)
|
||||
{
|
||||
u8 stride;
|
||||
u32 offset, val;
|
||||
|
||||
stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
|
||||
offset = reg_map[reg] + (stride * lch);
|
||||
val = __raw_readl(dma_base + offset);
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void omap2_disable_irq_lch(int lch)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = dma_read(IRQENABLE_L0, lch);
|
||||
val &= ~(1 << lch);
|
||||
dma_write(val, IRQENABLE_L0, lch);
|
||||
}
|
||||
|
||||
static void omap2_clear_dma(int lch)
|
||||
{
|
||||
int i = dma_common_ch_start;
|
||||
|
||||
for (; i <= dma_common_ch_end; i += 1)
|
||||
dma_write(0, i, lch);
|
||||
}
|
||||
|
||||
static void omap2_show_dma_caps(void)
|
||||
{
|
||||
u8 revision = dma_read(REVISION, 0) & 0xff;
|
||||
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
|
||||
revision >> 4, revision & 0xf);
|
||||
return;
|
||||
}
|
||||
|
||||
static u32 configure_dma_errata(void)
|
||||
{
|
||||
|
||||
/*
|
||||
* Errata applicable for OMAP2430ES1.0 and all omap2420
|
||||
*
|
||||
* I.
|
||||
* Erratum ID: Not Available
|
||||
* Inter Frame DMA buffering issue DMA will wrongly
|
||||
* buffer elements if packing and bursting is enabled. This might
|
||||
* result in data gets stalled in FIFO at the end of the block.
|
||||
* Workaround: DMA channels must have BUFFERING_DISABLED bit set to
|
||||
* guarantee no data will stay in the DMA FIFO in case inter frame
|
||||
* buffering occurs
|
||||
*
|
||||
* II.
|
||||
* Erratum ID: Not Available
|
||||
* DMA may hang when several channels are used in parallel
|
||||
* In the following configuration, DMA channel hanging can occur:
|
||||
* a. Channel i, hardware synchronized, is enabled
|
||||
* b. Another channel (Channel x), software synchronized, is enabled.
|
||||
* c. Channel i is disabled before end of transfer
|
||||
* d. Channel i is reenabled.
|
||||
* e. Steps 1 to 4 are repeated a certain number of times.
|
||||
* f. A third channel (Channel y), software synchronized, is enabled.
|
||||
* Channel x and Channel y may hang immediately after step 'f'.
|
||||
* Workaround:
|
||||
* For any channel used - make sure NextLCH_ID is set to the value j.
|
||||
*/
|
||||
if (cpu_is_omap2420() || (cpu_is_omap2430() &&
|
||||
(omap_type() == OMAP2430_REV_ES1_0))) {
|
||||
|
||||
SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
|
||||
SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
|
||||
}
|
||||
|
||||
/*
|
||||
* Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
|
||||
* after a transaction error.
|
||||
* Workaround: SW should explicitely disable the channel.
|
||||
*/
|
||||
if (cpu_class_is_omap2())
|
||||
SET_DMA_ERRATA(DMA_ERRATA_i378);
|
||||
|
||||
/*
|
||||
* Erratum ID: i541: sDMA FIFO draining does not finish
|
||||
* If sDMA channel is disabled on the fly, sDMA enters standby even
|
||||
* through FIFO Drain is still in progress
|
||||
* Workaround: Put sDMA in NoStandby more before a logical channel is
|
||||
* disabled, then put it back to SmartStandby right after the channel
|
||||
* finishes FIFO draining.
|
||||
*/
|
||||
if (cpu_is_omap34xx())
|
||||
SET_DMA_ERRATA(DMA_ERRATA_i541);
|
||||
|
||||
/*
|
||||
* Erratum ID: i88 : Special programming model needed to disable DMA
|
||||
* before end of block.
|
||||
* Workaround: software must ensure that the DMA is configured in No
|
||||
* Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
|
||||
*/
|
||||
if (omap_type() == OMAP3430_REV_ES1_0)
|
||||
SET_DMA_ERRATA(DMA_ERRATA_i88);
|
||||
|
||||
/*
|
||||
* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
|
||||
* read before the DMA controller finished disabling the channel.
|
||||
*/
|
||||
SET_DMA_ERRATA(DMA_ERRATA_3_3);
|
||||
|
||||
/*
|
||||
* Erratum ID: Not Available
|
||||
* A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
|
||||
* after secure sram context save and restore.
|
||||
* Work around: Hence we need to manually clear those IRQs to avoid
|
||||
* spurious interrupts. This affects only secure devices.
|
||||
*/
|
||||
if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
|
||||
SET_DMA_ERRATA(DMA_ROMCODE_BUG);
|
||||
|
||||
return errata;
|
||||
}
|
||||
|
||||
/* One time initializations */
|
||||
static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
||||
{
|
||||
struct omap_device *od;
|
||||
struct omap_system_dma_plat_info *p;
|
||||
struct resource *mem;
|
||||
char *name = "omap_dma_system";
|
||||
|
||||
dma_stride = OMAP2_DMA_STRIDE;
|
||||
dma_common_ch_start = CSDP;
|
||||
if (cpu_is_omap3630() || cpu_is_omap4430())
|
||||
dma_common_ch_end = CCDN;
|
||||
else
|
||||
dma_common_ch_end = CCFN;
|
||||
|
||||
p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
|
||||
if (!p) {
|
||||
pr_err("%s: Unable to allocate pdata for %s:%s\n",
|
||||
__func__, name, oh->name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
|
||||
p->disable_irq_lch = omap2_disable_irq_lch;
|
||||
p->show_dma_caps = omap2_show_dma_caps;
|
||||
p->clear_dma = omap2_clear_dma;
|
||||
p->dma_write = dma_write;
|
||||
p->dma_read = dma_read;
|
||||
|
||||
p->clear_lch_regs = NULL;
|
||||
|
||||
p->errata = configure_dma_errata();
|
||||
|
||||
od = omap_device_build(name, 0, oh, p, sizeof(*p),
|
||||
omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
|
||||
kfree(p);
|
||||
if (IS_ERR(od)) {
|
||||
pr_err("%s: Cant build omap_device for %s:%s.\n",
|
||||
__func__, name, oh->name);
|
||||
return IS_ERR(od);
|
||||
}
|
||||
|
||||
mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
dma_base = ioremap(mem->start, resource_size(mem));
|
||||
if (!dma_base) {
|
||||
dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
d = oh->dev_attr;
|
||||
d->chan = kzalloc(sizeof(struct omap_dma_lch) *
|
||||
(d->lch_count), GFP_KERNEL);
|
||||
|
||||
if (!d->chan) {
|
||||
dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init omap2_system_dma_init(void)
|
||||
{
|
||||
return omap_hwmod_for_each_by_class("dma",
|
||||
omap2_system_dma_init_dev, NULL);
|
||||
}
|
||||
arch_initcall(omap2_system_dma_init);
|
||||
@ -42,6 +42,7 @@ static struct omap_hwmod omap2420_gpio1_hwmod;
|
||||
static struct omap_hwmod omap2420_gpio2_hwmod;
|
||||
static struct omap_hwmod omap2420_gpio3_hwmod;
|
||||
static struct omap_hwmod omap2420_gpio4_hwmod;
|
||||
static struct omap_hwmod omap2420_dma_system_hwmod;
|
||||
|
||||
/* L3 -> L4_CORE interface */
|
||||
static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
|
||||
@ -779,6 +780,88 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* system dma */
|
||||
static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x002c,
|
||||
.syss_offs = 0x0028,
|
||||
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
|
||||
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
|
||||
SYSC_HAS_AUTOIDLE),
|
||||
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap2420_dma_hwmod_class = {
|
||||
.name = "dma",
|
||||
.sysc = &omap2420_dma_sysc,
|
||||
};
|
||||
|
||||
/* dma attributes */
|
||||
static struct omap_dma_dev_attr dma_dev_attr = {
|
||||
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
|
||||
IS_CSSA_32 | IS_CDSA_32,
|
||||
.lch_count = 32,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
|
||||
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
|
||||
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
|
||||
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
|
||||
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x4a0560ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* dma_system -> L3 */
|
||||
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
|
||||
.master = &omap2420_dma_system_hwmod,
|
||||
.slave = &omap2420_l3_main_hwmod,
|
||||
.clk = "core_l3_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* dma_system master ports */
|
||||
static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
|
||||
&omap2420_dma_system__l3,
|
||||
};
|
||||
|
||||
/* l4_core -> dma_system */
|
||||
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
|
||||
.master = &omap2420_l4_core_hwmod,
|
||||
.slave = &omap2420_dma_system_hwmod,
|
||||
.clk = "sdma_ick",
|
||||
.addr = omap2420_dma_system_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* dma_system slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
|
||||
&omap2420_l4_core__dma_system,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap2420_dma_system_hwmod = {
|
||||
.name = "dma",
|
||||
.class = &omap2420_dma_hwmod_class,
|
||||
.mpu_irqs = omap2420_dma_system_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
|
||||
.main_clk = "core_l3_ck",
|
||||
.slaves = omap2420_dma_system_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
|
||||
.masters = omap2420_dma_system_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
|
||||
.dev_attr = &dma_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap2420_hwmods[] = {
|
||||
&omap2420_l3_main_hwmod,
|
||||
&omap2420_l4_core_hwmod,
|
||||
@ -797,6 +880,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
|
||||
&omap2420_gpio2_hwmod,
|
||||
&omap2420_gpio3_hwmod,
|
||||
&omap2420_gpio4_hwmod,
|
||||
|
||||
/* dma_system class*/
|
||||
&omap2420_dma_system_hwmod,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
||||
@ -43,6 +43,7 @@ static struct omap_hwmod omap2430_gpio2_hwmod;
|
||||
static struct omap_hwmod omap2430_gpio3_hwmod;
|
||||
static struct omap_hwmod omap2430_gpio4_hwmod;
|
||||
static struct omap_hwmod omap2430_gpio5_hwmod;
|
||||
static struct omap_hwmod omap2430_dma_system_hwmod;
|
||||
|
||||
/* L3 -> L4_CORE interface */
|
||||
static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
|
||||
@ -838,6 +839,88 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* dma_system */
|
||||
static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x002c,
|
||||
.syss_offs = 0x0028,
|
||||
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
|
||||
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
|
||||
SYSC_HAS_AUTOIDLE),
|
||||
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap2430_dma_hwmod_class = {
|
||||
.name = "dma",
|
||||
.sysc = &omap2430_dma_sysc,
|
||||
};
|
||||
|
||||
/* dma attributes */
|
||||
static struct omap_dma_dev_attr dma_dev_attr = {
|
||||
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
|
||||
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
|
||||
.lch_count = 32,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
|
||||
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
|
||||
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
|
||||
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
|
||||
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x4a0560ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* dma_system -> L3 */
|
||||
static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
|
||||
.master = &omap2430_dma_system_hwmod,
|
||||
.slave = &omap2430_l3_main_hwmod,
|
||||
.clk = "core_l3_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* dma_system master ports */
|
||||
static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
|
||||
&omap2430_dma_system__l3,
|
||||
};
|
||||
|
||||
/* l4_core -> dma_system */
|
||||
static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
|
||||
.master = &omap2430_l4_core_hwmod,
|
||||
.slave = &omap2430_dma_system_hwmod,
|
||||
.clk = "sdma_ick",
|
||||
.addr = omap2430_dma_system_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* dma_system slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
|
||||
&omap2430_l4_core__dma_system,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap2430_dma_system_hwmod = {
|
||||
.name = "dma",
|
||||
.class = &omap2430_dma_hwmod_class,
|
||||
.mpu_irqs = omap2430_dma_system_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
|
||||
.main_clk = "core_l3_ck",
|
||||
.slaves = omap2430_dma_system_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
|
||||
.masters = omap2430_dma_system_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
|
||||
.dev_attr = &dma_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap2430_hwmods[] = {
|
||||
&omap2430_l3_main_hwmod,
|
||||
&omap2430_l4_core_hwmod,
|
||||
@ -857,6 +940,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
|
||||
&omap2430_gpio3_hwmod,
|
||||
&omap2430_gpio4_hwmod,
|
||||
&omap2430_gpio5_hwmod,
|
||||
|
||||
/* dma_system class*/
|
||||
&omap2430_dma_system_hwmod,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
||||
@ -52,6 +52,8 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod;
|
||||
static struct omap_hwmod omap3xxx_gpio5_hwmod;
|
||||
static struct omap_hwmod omap3xxx_gpio6_hwmod;
|
||||
|
||||
static struct omap_hwmod omap3xxx_dma_system_hwmod;
|
||||
|
||||
/* L3 -> L4_CORE interface */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
|
||||
.master = &omap3xxx_l3_main_hwmod,
|
||||
@ -1090,6 +1092,98 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* dma_system -> L3 */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
|
||||
.master = &omap3xxx_dma_system_hwmod,
|
||||
.slave = &omap3xxx_l3_main_hwmod,
|
||||
.clk = "core_l3_ick",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* dma attributes */
|
||||
static struct omap_dma_dev_attr dma_dev_attr = {
|
||||
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
|
||||
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
|
||||
.lch_count = 32,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x002c,
|
||||
.syss_offs = 0x0028,
|
||||
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
||||
SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
|
||||
SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
|
||||
.name = "dma",
|
||||
.sysc = &omap3xxx_dma_sysc,
|
||||
};
|
||||
|
||||
/* dma_system */
|
||||
static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
|
||||
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
|
||||
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
|
||||
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
|
||||
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48056000,
|
||||
.pa_end = 0x4a0560ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* dma_system master ports */
|
||||
static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
|
||||
&omap3xxx_dma_system__l3,
|
||||
};
|
||||
|
||||
/* l4_cfg -> dma_system */
|
||||
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap3xxx_dma_system_hwmod,
|
||||
.clk = "core_l4_ick",
|
||||
.addr = omap3xxx_dma_system_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* dma_system slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
|
||||
&omap3xxx_l4_core__dma_system,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_dma_system_hwmod = {
|
||||
.name = "dma",
|
||||
.class = &omap3xxx_dma_hwmod_class,
|
||||
.mpu_irqs = omap3xxx_dma_system_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
|
||||
.main_clk = "core_l3_ick",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP3430_ST_SDMA_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
|
||||
},
|
||||
},
|
||||
.slaves = omap3xxx_dma_system_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
|
||||
.masters = omap3xxx_dma_system_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
|
||||
.dev_attr = &dma_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
||||
&omap3xxx_l3_main_hwmod,
|
||||
&omap3xxx_l4_core_hwmod,
|
||||
@ -1113,6 +1207,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
||||
&omap3xxx_gpio4_hwmod,
|
||||
&omap3xxx_gpio5_hwmod,
|
||||
&omap3xxx_gpio6_hwmod,
|
||||
|
||||
/* dma_system class*/
|
||||
&omap3xxx_dma_system_hwmod,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/gpio.h>
|
||||
#include <plat/dma.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
@ -36,6 +37,7 @@
|
||||
#define OMAP44XX_DMA_REQ_START 1
|
||||
|
||||
/* Backward references (IPs with Bus Master capability) */
|
||||
static struct omap_hwmod omap44xx_dma_system_hwmod;
|
||||
static struct omap_hwmod omap44xx_dmm_hwmod;
|
||||
static struct omap_hwmod omap44xx_emif_fw_hwmod;
|
||||
static struct omap_hwmod omap44xx_l3_instr_hwmod;
|
||||
@ -216,6 +218,14 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* dma_system -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
|
||||
.master = &omap44xx_dma_system_hwmod,
|
||||
.slave = &omap44xx_l3_main_2_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
@ -226,6 +236,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
|
||||
|
||||
/* l3_main_2 slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
|
||||
&omap44xx_dma_system__l3_main_2,
|
||||
&omap44xx_l3_main_1__l3_main_2,
|
||||
&omap44xx_l4_cfg__l3_main_2,
|
||||
};
|
||||
@ -1376,6 +1387,93 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'dma' class
|
||||
* dma controller for data exchange between memory to memory (i.e. internal or
|
||||
* external memory) and gp peripherals to memory or memory to gp peripherals
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x002c,
|
||||
.syss_offs = 0x0028,
|
||||
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
||||
SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
|
||||
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
||||
SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
||||
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
/* dma attributes */
|
||||
static struct omap_dma_dev_attr dma_dev_attr = {
|
||||
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
|
||||
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
|
||||
.lch_count = 32,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
|
||||
.name = "dma",
|
||||
.sysc = &omap44xx_dma_sysc,
|
||||
};
|
||||
|
||||
/* dma_system */
|
||||
static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
|
||||
{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
|
||||
{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
|
||||
};
|
||||
|
||||
/* dma_system master ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
|
||||
&omap44xx_dma_system__l3_main_2,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4a056000,
|
||||
.pa_end = 0x4a0560ff,
|
||||
.flags = ADDR_TYPE_RT
|
||||
},
|
||||
};
|
||||
|
||||
/* l4_cfg -> dma_system */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
|
||||
.master = &omap44xx_l4_cfg_hwmod,
|
||||
.slave = &omap44xx_dma_system_hwmod,
|
||||
.clk = "l4_div_ck",
|
||||
.addr = omap44xx_dma_system_addrs,
|
||||
.addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* dma_system slave ports */
|
||||
static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
|
||||
&omap44xx_l4_cfg__dma_system,
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_dma_system_hwmod = {
|
||||
.name = "dma_system",
|
||||
.class = &omap44xx_dma_hwmod_class,
|
||||
.mpu_irqs = omap44xx_dma_system_irqs,
|
||||
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
|
||||
.main_clk = "l3_div_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
|
||||
},
|
||||
},
|
||||
.slaves = omap44xx_dma_system_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
|
||||
.masters = omap44xx_dma_system_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
|
||||
.dev_attr = &dma_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
|
||||
/* dmm class */
|
||||
&omap44xx_dmm_hwmod,
|
||||
@ -1391,6 +1489,10 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
|
||||
&omap44xx_l4_cfg_hwmod,
|
||||
&omap44xx_l4_per_hwmod,
|
||||
&omap44xx_l4_wkup_hwmod,
|
||||
|
||||
/* dma class */
|
||||
&omap44xx_dma_system_hwmod,
|
||||
|
||||
/* i2c class */
|
||||
&omap44xx_i2c1_hwmod,
|
||||
&omap44xx_i2c2_hwmod,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -21,142 +21,16 @@
|
||||
#ifndef __ASM_ARCH_DMA_H
|
||||
#define __ASM_ARCH_DMA_H
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
/*
|
||||
* TODO: These dma channel defines should go away once all
|
||||
* the omap drivers hwmod adapted.
|
||||
*/
|
||||
|
||||
/* Move omap4 specific defines to dma-44xx.h */
|
||||
#include "dma-44xx.h"
|
||||
|
||||
/* Hardware registers for omap1 */
|
||||
#define OMAP1_DMA_BASE (0xfffed800)
|
||||
|
||||
#define OMAP1_DMA_GCR 0x400
|
||||
#define OMAP1_DMA_GSCR 0x404
|
||||
#define OMAP1_DMA_GRST 0x408
|
||||
#define OMAP1_DMA_HW_ID 0x442
|
||||
#define OMAP1_DMA_PCH2_ID 0x444
|
||||
#define OMAP1_DMA_PCH0_ID 0x446
|
||||
#define OMAP1_DMA_PCH1_ID 0x448
|
||||
#define OMAP1_DMA_PCHG_ID 0x44a
|
||||
#define OMAP1_DMA_PCHD_ID 0x44c
|
||||
#define OMAP1_DMA_CAPS_0_U 0x44e
|
||||
#define OMAP1_DMA_CAPS_0_L 0x450
|
||||
#define OMAP1_DMA_CAPS_1_U 0x452
|
||||
#define OMAP1_DMA_CAPS_1_L 0x454
|
||||
#define OMAP1_DMA_CAPS_2 0x456
|
||||
#define OMAP1_DMA_CAPS_3 0x458
|
||||
#define OMAP1_DMA_CAPS_4 0x45a
|
||||
#define OMAP1_DMA_PCH2_SR 0x460
|
||||
#define OMAP1_DMA_PCH0_SR 0x480
|
||||
#define OMAP1_DMA_PCH1_SR 0x482
|
||||
#define OMAP1_DMA_PCHD_SR 0x4c0
|
||||
|
||||
/* Hardware registers for omap2 and omap3 */
|
||||
#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
|
||||
#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
|
||||
#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
|
||||
|
||||
#define OMAP_DMA4_REVISION 0x00
|
||||
#define OMAP_DMA4_GCR 0x78
|
||||
#define OMAP_DMA4_IRQSTATUS_L0 0x08
|
||||
#define OMAP_DMA4_IRQSTATUS_L1 0x0c
|
||||
#define OMAP_DMA4_IRQSTATUS_L2 0x10
|
||||
#define OMAP_DMA4_IRQSTATUS_L3 0x14
|
||||
#define OMAP_DMA4_IRQENABLE_L0 0x18
|
||||
#define OMAP_DMA4_IRQENABLE_L1 0x1c
|
||||
#define OMAP_DMA4_IRQENABLE_L2 0x20
|
||||
#define OMAP_DMA4_IRQENABLE_L3 0x24
|
||||
#define OMAP_DMA4_SYSSTATUS 0x28
|
||||
#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
|
||||
#define OMAP_DMA4_CAPS_0 0x64
|
||||
#define OMAP_DMA4_CAPS_2 0x6c
|
||||
#define OMAP_DMA4_CAPS_3 0x70
|
||||
#define OMAP_DMA4_CAPS_4 0x74
|
||||
|
||||
#define OMAP1_LOGICAL_DMA_CH_COUNT 17
|
||||
#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
|
||||
|
||||
/* Common channel specific registers for omap1 */
|
||||
#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
|
||||
#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
|
||||
#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
|
||||
#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
|
||||
#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
|
||||
#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
|
||||
#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
|
||||
#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
|
||||
#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
|
||||
#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
|
||||
#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
|
||||
#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
|
||||
#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
|
||||
#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
|
||||
#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
|
||||
|
||||
/* Common channel specific registers for omap2 */
|
||||
#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
|
||||
#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
|
||||
#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
|
||||
#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
|
||||
#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
|
||||
#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
|
||||
#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
|
||||
#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
|
||||
#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
|
||||
#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
|
||||
#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
|
||||
#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
|
||||
#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
|
||||
#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
|
||||
|
||||
/* Channel specific registers only on omap1 */
|
||||
#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
|
||||
#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
|
||||
#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
|
||||
#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
|
||||
#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
|
||||
#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
|
||||
#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
|
||||
#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
|
||||
#define OMAP1_DMA_CCEN(n) 0
|
||||
#define OMAP1_DMA_CCFN(n) 0
|
||||
|
||||
/* Channel specific registers only on omap2 */
|
||||
#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
|
||||
#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
|
||||
#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
|
||||
#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
|
||||
#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
|
||||
|
||||
/* Additional registers available on OMAP4 */
|
||||
#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
|
||||
#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
|
||||
#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
|
||||
|
||||
/* Dummy defines to keep multi-omap compiles happy */
|
||||
#define OMAP1_DMA_REVISION 0
|
||||
#define OMAP1_DMA_IRQSTATUS_L0 0
|
||||
#define OMAP1_DMA_IRQENABLE_L0 0
|
||||
#define OMAP1_DMA_OCP_SYSCONFIG 0
|
||||
#define OMAP_DMA4_HW_ID 0
|
||||
#define OMAP_DMA4_CAPS_0_L 0
|
||||
#define OMAP_DMA4_CAPS_0_U 0
|
||||
#define OMAP_DMA4_CAPS_1_L 0
|
||||
#define OMAP_DMA4_CAPS_1_U 0
|
||||
#define OMAP_DMA4_GSCR 0
|
||||
#define OMAP_DMA4_CPC(n) 0
|
||||
|
||||
#define OMAP_DMA4_LCH_CTRL(n) 0
|
||||
#define OMAP_DMA4_COLOR_L(n) 0
|
||||
#define OMAP_DMA4_COLOR_U(n) 0
|
||||
#define OMAP_DMA4_CCR2(n) 0
|
||||
#define OMAP1_DMA_CSSA(n) 0
|
||||
#define OMAP1_DMA_CDSA(n) 0
|
||||
#define OMAP_DMA4_CSSA_L(n) 0
|
||||
#define OMAP_DMA4_CSSA_U(n) 0
|
||||
#define OMAP_DMA4_CDSA_L(n) 0
|
||||
#define OMAP_DMA4_CDSA_U(n) 0
|
||||
#define OMAP1_DMA_COLOR(n) 0
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/* DMA channels for omap1 */
|
||||
#define OMAP_DMA_NO_DEVICE 0
|
||||
#define OMAP_DMA_MCSI1_TX 1
|
||||
@ -405,6 +279,63 @@
|
||||
#define DMA_CH_PRIO_HIGH 0x1
|
||||
#define DMA_CH_PRIO_LOW 0x0 /* Def */
|
||||
|
||||
/* Errata handling */
|
||||
#define IS_DMA_ERRATA(id) (errata & (id))
|
||||
#define SET_DMA_ERRATA(id) (errata |= (id))
|
||||
|
||||
#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
|
||||
#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
|
||||
#define DMA_ERRATA_i378 BIT(0x2)
|
||||
#define DMA_ERRATA_i541 BIT(0x3)
|
||||
#define DMA_ERRATA_i88 BIT(0x4)
|
||||
#define DMA_ERRATA_3_3 BIT(0x5)
|
||||
#define DMA_ROMCODE_BUG BIT(0x6)
|
||||
|
||||
/* Attributes for OMAP DMA Contrller */
|
||||
#define DMA_LINKED_LCH BIT(0x0)
|
||||
#define GLOBAL_PRIORITY BIT(0x1)
|
||||
#define RESERVE_CHANNEL BIT(0x2)
|
||||
#define IS_CSSA_32 BIT(0x3)
|
||||
#define IS_CDSA_32 BIT(0x4)
|
||||
#define IS_RW_PRIORITY BIT(0x5)
|
||||
#define ENABLE_1510_MODE BIT(0x6)
|
||||
#define SRC_PORT BIT(0x7)
|
||||
#define DST_PORT BIT(0x8)
|
||||
#define SRC_INDEX BIT(0x9)
|
||||
#define DST_INDEX BIT(0xA)
|
||||
#define IS_BURST_ONLY4 BIT(0xB)
|
||||
#define CLEAR_CSR_ON_READ BIT(0xC)
|
||||
#define IS_WORD_16 BIT(0xD)
|
||||
|
||||
enum omap_reg_offsets {
|
||||
|
||||
GCR, GSCR, GRST1, HW_ID,
|
||||
PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
|
||||
PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
|
||||
CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
|
||||
PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
|
||||
IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
|
||||
IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
|
||||
OCP_SYSCONFIG,
|
||||
|
||||
/* omap1+ specific */
|
||||
CPC, CCR2, LCH_CTRL,
|
||||
|
||||
/* Common registers for all omap's */
|
||||
CSDP, CCR, CICR, CSR,
|
||||
CEN, CFN, CSFI, CSEI,
|
||||
CSAC, CDAC, CDEI,
|
||||
CDFI, CLNK_CTRL,
|
||||
|
||||
/* Channel specific registers */
|
||||
CSSA, CDSA, COLOR,
|
||||
CCEN, CCFN,
|
||||
|
||||
/* omap3630 and omap4 specific */
|
||||
CDP, CNDP, CCDN,
|
||||
|
||||
};
|
||||
|
||||
enum omap_dma_burst_mode {
|
||||
OMAP_DMA_DATA_BURST_DIS = 0,
|
||||
OMAP_DMA_DATA_BURST_4,
|
||||
@ -470,6 +401,41 @@ struct omap_dma_channel_params {
|
||||
#endif
|
||||
};
|
||||
|
||||
struct omap_dma_lch {
|
||||
int next_lch;
|
||||
int dev_id;
|
||||
u16 saved_csr;
|
||||
u16 enabled_irqs;
|
||||
const char *dev_name;
|
||||
void (*callback)(int lch, u16 ch_status, void *data);
|
||||
void *data;
|
||||
long flags;
|
||||
/* required for Dynamic chaining */
|
||||
int prev_linked_ch;
|
||||
int next_linked_ch;
|
||||
int state;
|
||||
int chain_id;
|
||||
int status;
|
||||
};
|
||||
|
||||
struct omap_dma_dev_attr {
|
||||
u32 dev_caps;
|
||||
u16 lch_count;
|
||||
u16 chan_count;
|
||||
struct omap_dma_lch *chan;
|
||||
};
|
||||
|
||||
/* System DMA platform data structure */
|
||||
struct omap_system_dma_plat_info {
|
||||
struct omap_dma_dev_attr *dma_attr;
|
||||
u32 errata;
|
||||
void (*disable_irq_lch)(int lch);
|
||||
void (*show_dma_caps)(void);
|
||||
void (*clear_lch_regs)(int lch);
|
||||
void (*clear_dma)(int lch);
|
||||
void (*dma_write)(u32 val, int reg, int lch);
|
||||
u32 (*dma_read)(int reg, int lch);
|
||||
};
|
||||
|
||||
extern void omap_set_dma_priority(int lch, int dst_port, int priority);
|
||||
extern int omap_request_dma(int dev_id, const char *dev_name,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user