[MIPS] SMTC: The MT ASE requires to initialize c0_pagemask and c0_wired.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -1384,6 +1384,13 @@ void __init per_cpu_trap_init(void)
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cpu_cache_init();
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tlb_init();
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#ifdef CONFIG_MIPS_MT_SMTC
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} else if (!secondaryTC) {
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/*
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* First TC in non-boot VPE must do subset of tlb_init()
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* for MMU countrol registers.
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*/
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write_c0_pagemask(PM_DEFAULT_MASK);
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write_c0_wired(0);
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}
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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