s390/pci: provide support for MIO instructions
Provide support for PCI I/O instructions that work on mapped IO addresses. Signed-off-by: Sebastian Ott <sebott@linux.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Sebastian Ott
Martin Schwidefsky
parent
c475f1770a
commit
71ba41c9b1
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@ -30,14 +30,8 @@ void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
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#define ioremap_wc ioremap_nocache
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#define ioremap_wt ioremap_nocache
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static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
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{
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return (void __iomem *) offset;
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}
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static inline void iounmap(volatile void __iomem *addr)
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{
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}
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void __iomem *ioremap(unsigned long offset, unsigned long size);
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void iounmap(volatile void __iomem *addr);
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static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
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{
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@ -57,14 +51,17 @@ static inline void ioport_unmap(void __iomem *p)
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* the corresponding device and create the mapping cookie.
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*/
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#define pci_iomap pci_iomap
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#define pci_iomap_range pci_iomap_range
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#define pci_iounmap pci_iounmap
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#define pci_iomap_wc pci_iomap
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#define pci_iomap_wc_range pci_iomap_range
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#define pci_iomap_wc pci_iomap_wc
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#define pci_iomap_wc_range pci_iomap_wc_range
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#define memcpy_fromio(dst, src, count) zpci_memcpy_fromio(dst, src, count)
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#define memcpy_toio(dst, src, count) zpci_memcpy_toio(dst, src, count)
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#define memset_io(dst, val, count) zpci_memset_io(dst, val, count)
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#define mmiowb() zpci_barrier()
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#define __raw_readb zpci_read_u8
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#define __raw_readw zpci_read_u16
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#define __raw_readl zpci_read_u32
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@ -86,6 +86,8 @@ enum zpci_state {
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struct zpci_bar_struct {
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struct resource *res; /* bus resource */
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void __iomem *mio_wb;
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void __iomem *mio_wt;
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u32 val; /* bar start & 3 flag bits */
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u16 map_idx; /* index into bar mapping array */
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u8 size; /* order 2 exponent */
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@ -135,6 +137,7 @@ struct zpci_dev {
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struct iommu_device iommu_dev; /* IOMMU core handle */
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char res_name[16];
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bool mio_capable;
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struct zpci_bar_struct bars[PCI_BAR_COUNT];
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u64 start_dma; /* Start of available DMA addresses */
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@ -43,6 +43,8 @@ struct clp_fh_list_entry {
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#define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */
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#define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
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#define CLP_SET_ENABLE_MIO 2
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#define CLP_SET_DISABLE_MIO 3
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#define CLP_UTIL_STR_LEN 64
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#define CLP_PFIP_NR_SEGMENTS 4
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@ -80,7 +82,8 @@ struct clp_req_query_pci {
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struct clp_rsp_query_pci {
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struct clp_rsp_hdr hdr;
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u16 vfn; /* virtual fn number */
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u16 : 7;
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u16 : 6;
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u16 mio_addr_avail : 1;
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u16 util_str_avail : 1; /* utility string available? */
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u16 pfgid : 8; /* pci function group id */
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u32 fid; /* pci function id */
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@ -96,6 +99,15 @@ struct clp_rsp_query_pci {
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u32 reserved[11];
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u32 uid; /* user defined id */
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u8 util_str[CLP_UTIL_STR_LEN]; /* utility string */
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u32 reserved2[16];
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u32 mio_valid : 6;
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u32 : 26;
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u32 : 32;
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struct {
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u64 wb;
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u64 wt;
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} addr[PCI_BAR_COUNT];
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u32 reserved3[6];
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} __packed;
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/* Query PCI function group request */
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@ -2,6 +2,8 @@
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#ifndef _ASM_S390_PCI_INSN_H
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#define _ASM_S390_PCI_INSN_H
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#include <linux/jump_label.h>
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/* Load/Store status codes */
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#define ZPCI_PCI_ST_FUNC_NOT_ENABLED 4
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#define ZPCI_PCI_ST_FUNC_IN_ERR 8
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@ -122,6 +124,8 @@ union zpci_sic_iib {
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struct zpci_cdiib cdiib;
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};
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DECLARE_STATIC_KEY_FALSE(have_mio);
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u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status);
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int zpci_refresh_trans(u64 fn, u64 addr, u64 range);
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int __zpci_load(u64 *data, u64 req, u64 offset);
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@ -129,6 +133,7 @@ int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len);
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int __zpci_store(u64 data, u64 req, u64 offset);
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int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len);
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int __zpci_store_block(const u64 *data, u64 req, u64 offset);
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void zpci_barrier(void);
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int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib);
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static inline int zpci_set_irq_ctrl(u16 ctl, u8 isc)
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@ -25,6 +25,7 @@
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#include <linux/export.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/jump_label.h>
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#include <linux/pci.h>
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#include <asm/isc.h>
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@ -50,6 +51,8 @@ static unsigned long *zpci_iomap_bitmap;
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struct zpci_iomap_entry *zpci_iomap_start;
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EXPORT_SYMBOL_GPL(zpci_iomap_start);
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DEFINE_STATIC_KEY_FALSE(have_mio);
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static struct kmem_cache *zdev_fmb_cache;
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struct zpci_dev *get_zdev_by_fid(u32 fid)
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@ -223,18 +226,48 @@ void __iowrite64_copy(void __iomem *to, const void *from, size_t count)
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zpci_memcpy_toio(to, from, count);
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}
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void __iomem *ioremap(unsigned long ioaddr, unsigned long size)
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{
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struct vm_struct *area;
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unsigned long offset;
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if (!size)
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return NULL;
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if (!static_branch_unlikely(&have_mio))
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return (void __iomem *) ioaddr;
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offset = ioaddr & ~PAGE_MASK;
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ioaddr &= PAGE_MASK;
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size = PAGE_ALIGN(size + offset);
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area = get_vm_area(size, VM_IOREMAP);
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if (!area)
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return NULL;
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if (ioremap_page_range((unsigned long) area->addr,
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(unsigned long) area->addr + size,
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ioaddr, PAGE_KERNEL)) {
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vunmap(area->addr);
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return NULL;
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}
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return (void __iomem *) ((unsigned long) area->addr + offset);
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}
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EXPORT_SYMBOL(ioremap);
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void iounmap(volatile void __iomem *addr)
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{
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if (static_branch_likely(&have_mio))
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vunmap((__force void *) ((unsigned long) addr & PAGE_MASK));
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}
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EXPORT_SYMBOL(iounmap);
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/* Create a virtual mapping cookie for a PCI BAR */
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void __iomem *pci_iomap_range(struct pci_dev *pdev,
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int bar,
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unsigned long offset,
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unsigned long max)
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static void __iomem *pci_iomap_range_fh(struct pci_dev *pdev, int bar,
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unsigned long offset, unsigned long max)
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{
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struct zpci_dev *zdev = to_zpci(pdev);
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int idx;
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if (!pci_resource_len(pdev, bar) || bar >= PCI_BAR_COUNT)
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return NULL;
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idx = zdev->bars[bar].map_idx;
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spin_lock(&zpci_iomap_lock);
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/* Detect overrun */
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@ -245,6 +278,30 @@ void __iomem *pci_iomap_range(struct pci_dev *pdev,
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return (void __iomem *) ZPCI_ADDR(idx) + offset;
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}
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static void __iomem *pci_iomap_range_mio(struct pci_dev *pdev, int bar,
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unsigned long offset,
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unsigned long max)
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{
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unsigned long barsize = pci_resource_len(pdev, bar);
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struct zpci_dev *zdev = to_zpci(pdev);
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void __iomem *iova;
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iova = ioremap((unsigned long) zdev->bars[bar].mio_wt, barsize);
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return iova ? iova + offset : iova;
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}
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void __iomem *pci_iomap_range(struct pci_dev *pdev, int bar,
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unsigned long offset, unsigned long max)
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{
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if (!pci_resource_len(pdev, bar) || bar >= PCI_BAR_COUNT)
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return NULL;
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if (static_branch_likely(&have_mio))
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return pci_iomap_range_mio(pdev, bar, offset, max);
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else
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return pci_iomap_range_fh(pdev, bar, offset, max);
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}
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EXPORT_SYMBOL(pci_iomap_range);
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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@ -253,7 +310,37 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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}
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EXPORT_SYMBOL(pci_iomap);
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void pci_iounmap(struct pci_dev *pdev, void __iomem *addr)
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static void __iomem *pci_iomap_wc_range_mio(struct pci_dev *pdev, int bar,
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unsigned long offset, unsigned long max)
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{
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unsigned long barsize = pci_resource_len(pdev, bar);
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struct zpci_dev *zdev = to_zpci(pdev);
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void __iomem *iova;
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iova = ioremap((unsigned long) zdev->bars[bar].mio_wb, barsize);
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return iova ? iova + offset : iova;
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}
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void __iomem *pci_iomap_wc_range(struct pci_dev *pdev, int bar,
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unsigned long offset, unsigned long max)
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{
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if (!pci_resource_len(pdev, bar) || bar >= PCI_BAR_COUNT)
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return NULL;
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if (static_branch_likely(&have_mio))
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return pci_iomap_wc_range_mio(pdev, bar, offset, max);
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else
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return pci_iomap_range_fh(pdev, bar, offset, max);
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}
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EXPORT_SYMBOL(pci_iomap_wc_range);
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void __iomem *pci_iomap_wc(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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return pci_iomap_wc_range(dev, bar, 0, maxlen);
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}
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EXPORT_SYMBOL(pci_iomap_wc);
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static void pci_iounmap_fh(struct pci_dev *pdev, void __iomem *addr)
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{
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unsigned int idx = ZPCI_IDX(addr);
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@ -266,6 +353,19 @@ void pci_iounmap(struct pci_dev *pdev, void __iomem *addr)
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}
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spin_unlock(&zpci_iomap_lock);
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}
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static void pci_iounmap_mio(struct pci_dev *pdev, void __iomem *addr)
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{
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iounmap(addr);
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}
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void pci_iounmap(struct pci_dev *pdev, void __iomem *addr)
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{
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if (static_branch_likely(&have_mio))
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pci_iounmap_mio(pdev, addr);
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else
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pci_iounmap_fh(pdev, addr);
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}
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EXPORT_SYMBOL(pci_iounmap);
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static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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@ -312,6 +412,7 @@ static struct resource iov_res = {
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static void zpci_map_resources(struct pci_dev *pdev)
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{
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struct zpci_dev *zdev = to_zpci(pdev);
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resource_size_t len;
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int i;
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@ -319,6 +420,11 @@ static void zpci_map_resources(struct pci_dev *pdev)
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len = pci_resource_len(pdev, i);
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if (!len)
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continue;
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if (static_branch_likely(&have_mio))
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pdev->resource[i].start =
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(resource_size_t __force) zdev->bars[i].mio_wb;
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else
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pdev->resource[i].start =
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(resource_size_t __force) pci_iomap(pdev, i, 0);
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pdev->resource[i].end = pdev->resource[i].start + len - 1;
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@ -341,6 +447,9 @@ static void zpci_unmap_resources(struct pci_dev *pdev)
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resource_size_t len;
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int i;
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if (static_branch_likely(&have_mio))
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return;
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for (i = 0; i < PCI_BAR_COUNT; i++) {
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len = pci_resource_len(pdev, i);
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if (!len)
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@ -772,6 +881,9 @@ static int __init pci_base_init(void)
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if (!test_facility(69) || !test_facility(71))
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return 0;
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if (test_facility(153))
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static_branch_enable(&have_mio);
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rc = zpci_debug_init();
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if (rc)
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goto out;
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@ -163,7 +163,14 @@ static int clp_store_query_pci_fn(struct zpci_dev *zdev,
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memcpy(zdev->util_str, response->util_str,
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sizeof(zdev->util_str));
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}
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zdev->mio_capable = response->mio_addr_avail;
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for (i = 0; i < PCI_BAR_COUNT; i++) {
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if (!(response->mio_valid & (1 << (PCI_BAR_COUNT - i - 1))))
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continue;
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zdev->bars[i].mio_wb = (void __iomem *) response->addr[i].wb;
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zdev->bars[i].mio_wt = (void __iomem *) response->addr[i].wt;
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}
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return 0;
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}
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@ -279,11 +286,18 @@ int clp_enable_fh(struct zpci_dev *zdev, u8 nr_dma_as)
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int rc;
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rc = clp_set_pci_fn(&fh, nr_dma_as, CLP_SET_ENABLE_PCI_FN);
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if (!rc)
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/* Success -> store enabled handle in zdev */
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zdev->fh = fh;
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zpci_dbg(3, "ena fid:%x, fh:%x, rc:%d\n", zdev->fid, fh, rc);
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if (rc)
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goto out;
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zpci_dbg(3, "ena fid:%x, fh:%x, rc:%d\n", zdev->fid, zdev->fh, rc);
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zdev->fh = fh;
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if (zdev->mio_capable) {
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rc = clp_set_pci_fn(&fh, nr_dma_as, CLP_SET_ENABLE_MIO);
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zpci_dbg(3, "ena mio fid:%x, fh:%x, rc:%d\n", zdev->fid, fh, rc);
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if (rc)
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clp_disable_fh(zdev);
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}
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out:
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return rc;
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}
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@ -296,11 +310,10 @@ int clp_disable_fh(struct zpci_dev *zdev)
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return 0;
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rc = clp_set_pci_fn(&fh, 0, CLP_SET_DISABLE_PCI_FN);
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zpci_dbg(3, "dis fid:%x, fh:%x, rc:%d\n", zdev->fid, fh, rc);
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if (!rc)
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/* Success -> store disabled handle in zdev */
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zdev->fh = fh;
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zpci_dbg(3, "dis fid:%x, fh:%x, rc:%d\n", zdev->fid, zdev->fh, rc);
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return rc;
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}
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@ -8,6 +8,7 @@
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#include <linux/export.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/jump_label.h>
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#include <asm/facility.h>
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#include <asm/pci_insn.h>
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#include <asm/pci_debug.h>
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@ -161,13 +162,50 @@ int __zpci_load(u64 *data, u64 req, u64 offset)
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}
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EXPORT_SYMBOL_GPL(__zpci_load);
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int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len)
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static inline int zpci_load_fh(u64 *data, const volatile void __iomem *addr,
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unsigned long len)
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{
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struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
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u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, len);
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return __zpci_load(data, req, ZPCI_OFFSET(addr));
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}
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static inline int __pcilg_mio(u64 *data, u64 ioaddr, u64 len, u8 *status)
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{
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register u64 addr asm("2") = ioaddr;
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register u64 r3 asm("3") = len;
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int cc = -ENXIO;
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u64 __data;
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asm volatile (
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" .insn rre,0xb9d60000,%[data],%[ioaddr]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [data] "=d" (__data), "+d" (r3)
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: [ioaddr] "d" (addr)
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: "cc");
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*status = r3 >> 24 & 0xff;
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*data = __data;
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return cc;
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}
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|
||||
int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len)
|
||||
{
|
||||
u8 status;
|
||||
int cc;
|
||||
|
||||
if (!static_branch_unlikely(&have_mio))
|
||||
return zpci_load_fh(data, addr, len);
|
||||
|
||||
cc = __pcilg_mio(data, (__force u64) addr, len, &status);
|
||||
if (cc)
|
||||
zpci_err_insn(cc, status, 0, (__force u64) addr);
|
||||
|
||||
return (cc > 0) ? -EIO : cc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(zpci_load);
|
||||
|
||||
/* PCI Store */
|
||||
|
|
@ -208,13 +246,48 @@ int __zpci_store(u64 data, u64 req, u64 offset)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(__zpci_store);
|
||||
|
||||
int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len)
|
||||
static inline int zpci_store_fh(const volatile void __iomem *addr, u64 data,
|
||||
unsigned long len)
|
||||
{
|
||||
struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
|
||||
u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, len);
|
||||
|
||||
return __zpci_store(data, req, ZPCI_OFFSET(addr));
|
||||
}
|
||||
|
||||
static inline int __pcistg_mio(u64 data, u64 ioaddr, u64 len, u8 *status)
|
||||
{
|
||||
register u64 addr asm("2") = ioaddr;
|
||||
register u64 r3 asm("3") = len;
|
||||
int cc = -ENXIO;
|
||||
|
||||
asm volatile (
|
||||
" .insn rre,0xb9d40000,%[data],%[ioaddr]\n"
|
||||
"0: ipm %[cc]\n"
|
||||
" srl %[cc],28\n"
|
||||
"1:\n"
|
||||
EX_TABLE(0b, 1b)
|
||||
: [cc] "+d" (cc), "+d" (r3)
|
||||
: [data] "d" (data), [ioaddr] "d" (addr)
|
||||
: "cc");
|
||||
*status = r3 >> 24 & 0xff;
|
||||
return cc;
|
||||
}
|
||||
|
||||
int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len)
|
||||
{
|
||||
u8 status;
|
||||
int cc;
|
||||
|
||||
if (!static_branch_unlikely(&have_mio))
|
||||
return zpci_store_fh(addr, data, len);
|
||||
|
||||
cc = __pcistg_mio(data, (__force u64) addr, len, &status);
|
||||
if (cc)
|
||||
zpci_err_insn(cc, status, 0, (__force u64) addr);
|
||||
|
||||
return (cc > 0) ? -EIO : cc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(zpci_store);
|
||||
|
||||
/* PCI Store Block */
|
||||
|
|
@ -253,7 +326,7 @@ int __zpci_store_block(const u64 *data, u64 req, u64 offset)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(__zpci_store_block);
|
||||
|
||||
int zpci_write_block(volatile void __iomem *dst,
|
||||
static inline int zpci_write_block_fh(volatile void __iomem *dst,
|
||||
const void *src, unsigned long len)
|
||||
{
|
||||
struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(dst)];
|
||||
|
|
@ -262,4 +335,52 @@ int zpci_write_block(volatile void __iomem *dst,
|
|||
|
||||
return __zpci_store_block(src, req, offset);
|
||||
}
|
||||
|
||||
static inline int __pcistb_mio(const u64 *data, u64 ioaddr, u64 len, u8 *status)
|
||||
{
|
||||
int cc = -ENXIO;
|
||||
|
||||
asm volatile (
|
||||
" .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[data]\n"
|
||||
"0: ipm %[cc]\n"
|
||||
" srl %[cc],28\n"
|
||||
"1:\n"
|
||||
EX_TABLE(0b, 1b)
|
||||
: [cc] "+d" (cc), [len] "+d" (len)
|
||||
: [ioaddr] "d" (ioaddr), [data] "Q" (*data)
|
||||
: "cc");
|
||||
*status = len >> 24 & 0xff;
|
||||
return cc;
|
||||
}
|
||||
|
||||
int zpci_write_block(volatile void __iomem *dst,
|
||||
const void *src, unsigned long len)
|
||||
{
|
||||
u8 status;
|
||||
int cc;
|
||||
|
||||
if (!static_branch_unlikely(&have_mio))
|
||||
return zpci_write_block_fh(dst, src, len);
|
||||
|
||||
cc = __pcistb_mio(src, (__force u64) dst, len, &status);
|
||||
if (cc)
|
||||
zpci_err_insn(cc, status, 0, (__force u64) dst);
|
||||
|
||||
return (cc > 0) ? -EIO : cc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(zpci_write_block);
|
||||
|
||||
static inline void __pciwb_mio(void)
|
||||
{
|
||||
unsigned long unused = 0;
|
||||
|
||||
asm volatile (".insn rre,0xb9d50000,%[op],%[op]\n"
|
||||
: [op] "+d" (unused));
|
||||
}
|
||||
|
||||
void zpci_barrier(void)
|
||||
{
|
||||
if (static_branch_likely(&have_mio))
|
||||
__pciwb_mio();
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(zpci_barrier);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user