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powerpc: Optimise smp_wmb on 64-bit processors

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For 64-bit processors, lwsync is the recommended method of store/store
ordering on caching enabled memory.  For those subarchs which have
lwsync, use it rather than eieio for smp_wmb.

Signed-off-by: Nick Piggin <npiggin@suse.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Nick Piggin 2008-05-22 00:12:31 +10:00 committed by Paul Mackerras
parent e9a4b6a3f6
commit 74f0609526
1 changed files with 10 additions and 3 deletions
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13
include/asm-powerpc/system.h
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@ -30,8 +30,8 @@
*
* For wmb(), we use sync since wmb is used in drivers to order
* stores to system memory with respect to writes to the device.
* However, smp_wmb() can be a lighter-weight eieio barrier on
* SMP since it is only used to order updates to system memory.
* However, smp_wmb() can be a lighter-weight lwsync or eieio barrier
* on SMP since it is only used to order updates to system memory.
*/
#define mb() __asm__ __volatile__ ("sync" : : : "memory")
#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
@ -43,9 +43,16 @@
#ifdef __KERNEL__
#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
#ifdef CONFIG_SMP
#ifdef __SUBARCH_HAS_LWSYNC
# define SMPWMB lwsync
#else
# define SMPWMB eieio
#endif
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() eieio()
#define smp_wmb() __asm__ __volatile__ (__stringify(SMPWMB) : : :"memory")
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()