x86/retpoline: Add initial retpoline support
Enable the use of -mindirect-branch=thunk-extern in newer GCC, and provide the corresponding thunks. Provide assembler macros for invoking the thunks in the same way that GCC does, from native and inline assembler. This adds X86_FEATURE_RETPOLINE and sets it by default on all CPUs. In some circumstances, IBRS microcode features may be used instead, and the retpoline can be disabled. On AMD CPUs if lfence is serialising, the retpoline can be dramatically simplified to a simple "lfence; jmp *\reg". A future patch, after it has been verified that lfence really is serialising in all circumstances, can enable this by setting the X86_FEATURE_RETPOLINE_AMD feature bit in addition to X86_FEATURE_RETPOLINE. Do not align the retpoline in the altinstr section, because there is no guarantee that it stays aligned when it's copied over the oldinstr during alternative patching. [ Andi Kleen: Rename the macros, add CONFIG_RETPOLINE option, export thunks] [ tglx: Put actual function CALL/JMP in front of the macros, convert to symbolic labels ] [ dwmw2: Convert back to numeric labels, merge objtool fixes ] Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Arjan van de Ven <arjan@linux.intel.com> Acked-by: Ingo Molnar <mingo@kernel.org> Cc: gnomes@lxorguk.ukuu.org.uk Cc: Rik van Riel <riel@redhat.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: thomas.lendacky@amd.com Cc: Peter Zijlstra <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Jiri Kosina <jikos@kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Kees Cook <keescook@google.com> Cc: Tim Chen <tim.c.chen@linux.intel.com> Cc: Greg Kroah-Hartman <gregkh@linux-foundation.org> Cc: Paul Turner <pjt@google.com> Link: https://lkml.kernel.org/r/1515707194-20531-4-git-send-email-dwmw@amazon.co.uk
This commit is contained in:
David Woodhouse
Thomas Gleixner
parent
258c76059c
commit
76b043848f
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@ -429,6 +429,19 @@ config GOLDFISH
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def_bool y
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def_bool y
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depends on X86_GOLDFISH
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depends on X86_GOLDFISH
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config RETPOLINE
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bool "Avoid speculative indirect branches in kernel"
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default y
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help
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Compile kernel with the retpoline compiler options to guard against
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kernel-to-user data leaks by avoiding speculative indirect
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branches. Requires a compiler with -mindirect-branch=thunk-extern
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support for full protection. The kernel may run slower.
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Without compiler support, at least indirect branches in assembler
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code are eliminated. Since this includes the syscall entry path,
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it is not entirely pointless.
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config INTEL_RDT
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config INTEL_RDT
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bool "Intel Resource Director Technology support"
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bool "Intel Resource Director Technology support"
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default n
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default n
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@ -235,6 +235,16 @@ KBUILD_CFLAGS += -Wno-sign-compare
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#
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#
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KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
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KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
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# Avoid indirect branches in kernel to deal with Spectre
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ifdef CONFIG_RETPOLINE
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RETPOLINE_CFLAGS += $(call cc-option,-mindirect-branch=thunk-extern -mindirect-branch-register)
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ifneq ($(RETPOLINE_CFLAGS),)
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KBUILD_CFLAGS += $(RETPOLINE_CFLAGS) -DRETPOLINE
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else
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$(warning CONFIG_RETPOLINE=y, but not supported by the compiler. Toolchain update recommended.)
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endif
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endif
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archscripts: scripts_basic
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archscripts: scripts_basic
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$(Q)$(MAKE) $(build)=arch/x86/tools relocs
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$(Q)$(MAKE) $(build)=arch/x86/tools relocs
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@ -11,7 +11,32 @@
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#include <asm/pgtable.h>
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#include <asm/pgtable.h>
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#include <asm/special_insns.h>
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#include <asm/special_insns.h>
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#include <asm/preempt.h>
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#include <asm/preempt.h>
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#include <asm/asm.h>
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#ifndef CONFIG_X86_CMPXCHG64
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#ifndef CONFIG_X86_CMPXCHG64
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extern void cmpxchg8b_emu(void);
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extern void cmpxchg8b_emu(void);
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#endif
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#endif
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#ifdef CONFIG_RETPOLINE
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#ifdef CONFIG_X86_32
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#define INDIRECT_THUNK(reg) extern asmlinkage void __x86_indirect_thunk_e ## reg(void);
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#else
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#define INDIRECT_THUNK(reg) extern asmlinkage void __x86_indirect_thunk_r ## reg(void);
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INDIRECT_THUNK(8)
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INDIRECT_THUNK(9)
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INDIRECT_THUNK(10)
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INDIRECT_THUNK(11)
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INDIRECT_THUNK(12)
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INDIRECT_THUNK(13)
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INDIRECT_THUNK(14)
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INDIRECT_THUNK(15)
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#endif
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INDIRECT_THUNK(ax)
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INDIRECT_THUNK(bx)
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INDIRECT_THUNK(cx)
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INDIRECT_THUNK(dx)
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INDIRECT_THUNK(si)
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INDIRECT_THUNK(di)
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INDIRECT_THUNK(bp)
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INDIRECT_THUNK(sp)
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#endif /* CONFIG_RETPOLINE */
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@ -203,6 +203,8 @@
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
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#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
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#define X86_FEATURE_RETPOLINE ( 7*32+12) /* Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
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#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
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#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
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#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
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#define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */
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128
arch/x86/include/asm/nospec-branch.h
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128
arch/x86/include/asm/nospec-branch.h
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@ -0,0 +1,128 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __NOSPEC_BRANCH_H__
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#define __NOSPEC_BRANCH_H__
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#include <asm/alternative.h>
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#include <asm/alternative-asm.h>
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#include <asm/cpufeatures.h>
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#ifdef __ASSEMBLY__
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/*
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* This should be used immediately before a retpoline alternative. It tells
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* objtool where the retpolines are so that it can make sense of the control
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* flow by just reading the original instruction(s) and ignoring the
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* alternatives.
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*/
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.macro ANNOTATE_NOSPEC_ALTERNATIVE
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.Lannotate_\@:
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.pushsection .discard.nospec
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.long .Lannotate_\@ - .
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.popsection
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.endm
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/*
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* These are the bare retpoline primitives for indirect jmp and call.
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* Do not use these directly; they only exist to make the ALTERNATIVE
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* invocation below less ugly.
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*/
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.macro RETPOLINE_JMP reg:req
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call .Ldo_rop_\@
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.Lspec_trap_\@:
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pause
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jmp .Lspec_trap_\@
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.Ldo_rop_\@:
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mov \reg, (%_ASM_SP)
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ret
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.endm
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/*
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* This is a wrapper around RETPOLINE_JMP so the called function in reg
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* returns to the instruction after the macro.
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*/
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.macro RETPOLINE_CALL reg:req
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jmp .Ldo_call_\@
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.Ldo_retpoline_jmp_\@:
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RETPOLINE_JMP \reg
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.Ldo_call_\@:
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call .Ldo_retpoline_jmp_\@
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.endm
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/*
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* JMP_NOSPEC and CALL_NOSPEC macros can be used instead of a simple
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* indirect jmp/call which may be susceptible to the Spectre variant 2
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* attack.
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*/
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.macro JMP_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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ANNOTATE_NOSPEC_ALTERNATIVE
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ALTERNATIVE_2 __stringify(jmp *\reg), \
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__stringify(RETPOLINE_JMP \reg), X86_FEATURE_RETPOLINE, \
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__stringify(lfence; jmp *\reg), X86_FEATURE_RETPOLINE_AMD
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#else
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jmp *\reg
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#endif
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.endm
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.macro CALL_NOSPEC reg:req
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#ifdef CONFIG_RETPOLINE
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ANNOTATE_NOSPEC_ALTERNATIVE
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ALTERNATIVE_2 __stringify(call *\reg), \
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__stringify(RETPOLINE_CALL \reg), X86_FEATURE_RETPOLINE,\
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__stringify(lfence; call *\reg), X86_FEATURE_RETPOLINE_AMD
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#else
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call *\reg
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#endif
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.endm
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#else /* __ASSEMBLY__ */
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#define ANNOTATE_NOSPEC_ALTERNATIVE \
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"999:\n\t" \
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".pushsection .discard.nospec\n\t" \
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".long 999b - .\n\t" \
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".popsection\n\t"
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#if defined(CONFIG_X86_64) && defined(RETPOLINE)
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/*
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* Since the inline asm uses the %V modifier which is only in newer GCC,
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* the 64-bit one is dependent on RETPOLINE not CONFIG_RETPOLINE.
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*/
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# define CALL_NOSPEC \
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ANNOTATE_NOSPEC_ALTERNATIVE \
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ALTERNATIVE( \
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"call *%[thunk_target]\n", \
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"call __x86_indirect_thunk_%V[thunk_target]\n", \
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X86_FEATURE_RETPOLINE)
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# define THUNK_TARGET(addr) [thunk_target] "r" (addr)
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#elif defined(CONFIG_X86_32) && defined(CONFIG_RETPOLINE)
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/*
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* For i386 we use the original ret-equivalent retpoline, because
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* otherwise we'll run out of registers. We don't care about CET
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* here, anyway.
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*/
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# define CALL_NOSPEC ALTERNATIVE("call *%[thunk_target]\n", \
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" jmp 904f;\n" \
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" .align 16\n" \
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"901: call 903f;\n" \
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"902: pause;\n" \
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" jmp 902b;\n" \
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" .align 16\n" \
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"903: addl $4, %%esp;\n" \
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" pushl %[thunk_target];\n" \
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" ret;\n" \
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" .align 16\n" \
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"904: call 901b;\n", \
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X86_FEATURE_RETPOLINE)
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# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
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#else /* No retpoline */
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# define CALL_NOSPEC "call *%[thunk_target]\n"
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# define THUNK_TARGET(addr) [thunk_target] "rm" (addr)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __NOSPEC_BRANCH_H__ */
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@ -905,6 +905,10 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
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setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
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setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
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setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
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setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
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#ifdef CONFIG_RETPOLINE
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setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
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#endif
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fpu__init_system(c);
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fpu__init_system(c);
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#ifdef CONFIG_X86_32
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#ifdef CONFIG_X86_32
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@ -26,6 +26,7 @@ lib-y += memcpy_$(BITS).o
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lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem.o
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lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem.o
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lib-$(CONFIG_INSTRUCTION_DECODER) += insn.o inat.o
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lib-$(CONFIG_INSTRUCTION_DECODER) += insn.o inat.o
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lib-$(CONFIG_RANDOMIZE_BASE) += kaslr.o
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lib-$(CONFIG_RANDOMIZE_BASE) += kaslr.o
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lib-$(CONFIG_RETPOLINE) += retpoline.o
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obj-y += msr.o msr-reg.o msr-reg-export.o hweight.o
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obj-y += msr.o msr-reg.o msr-reg-export.o hweight.o
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48
arch/x86/lib/retpoline.S
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48
arch/x86/lib/retpoline.S
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@ -0,0 +1,48 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/stringify.h>
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#include <linux/linkage.h>
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#include <asm/dwarf2.h>
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#include <asm/cpufeatures.h>
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#include <asm/alternative-asm.h>
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#include <asm/export.h>
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#include <asm/nospec-branch.h>
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.macro THUNK reg
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.section .text.__x86.indirect_thunk.\reg
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ENTRY(__x86_indirect_thunk_\reg)
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CFI_STARTPROC
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JMP_NOSPEC %\reg
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CFI_ENDPROC
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ENDPROC(__x86_indirect_thunk_\reg)
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.endm
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/*
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* Despite being an assembler file we can't just use .irp here
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* because __KSYM_DEPS__ only uses the C preprocessor and would
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* only see one instance of "__x86_indirect_thunk_\reg" rather
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* than one per register with the correct names. So we do it
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* the simple and nasty way...
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*/
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#define EXPORT_THUNK(reg) EXPORT_SYMBOL(__x86_indirect_thunk_ ## reg)
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#define GENERATE_THUNK(reg) THUNK reg ; EXPORT_THUNK(reg)
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GENERATE_THUNK(_ASM_AX)
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GENERATE_THUNK(_ASM_BX)
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GENERATE_THUNK(_ASM_CX)
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GENERATE_THUNK(_ASM_DX)
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GENERATE_THUNK(_ASM_SI)
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GENERATE_THUNK(_ASM_DI)
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GENERATE_THUNK(_ASM_BP)
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GENERATE_THUNK(_ASM_SP)
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#ifdef CONFIG_64BIT
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GENERATE_THUNK(r8)
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GENERATE_THUNK(r9)
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GENERATE_THUNK(r10)
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GENERATE_THUNK(r11)
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GENERATE_THUNK(r12)
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GENERATE_THUNK(r13)
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GENERATE_THUNK(r14)
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GENERATE_THUNK(r15)
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#endif
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