mmc: sdhci-omap: Workaround for Errata i802
Errata i802 in AM572x Sitara Processors Silicon Revision 2.0, 1.1 (SPRZ429K July 2014–Revised March 2017 [1]) mentions DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure and it has to be disabled during the tuning procedure Implement workaround for Errata i802 here.. [1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -257,6 +257,7 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
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u32 start_window = 0, max_window = 0;
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u8 cur_match, prev_match = 0;
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u32 length = 0, max_len = 0;
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u32 ier = host->ier;
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u32 phase_delay = 0;
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int ret = 0;
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u32 reg;
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@ -277,6 +278,16 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
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reg |= DLL_SWT;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
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/*
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* OMAP5/DRA74X/DRA72x Errata i802:
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* DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
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* during the tuning procedure. So disable it during the
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* tuning procedure.
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*/
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ier &= ~SDHCI_INT_DATA_CRC;
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sdhci_writel(host, ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
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while (phase_delay <= MAX_PHASE_DELAY) {
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sdhci_omap_set_dll(omap_host, phase_delay);
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@ -322,6 +333,8 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
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ret:
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sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
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sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
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return ret;
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}
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