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clocksource: sun4i: Fix bug when switching from periodic to oneshot modes

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The interval was firing at was set up at probe time, and only changed in
the set_next_event, and never changed back, which is not really what is
expected.

When enabling the periodic mode, now set an interval to tick every
jiffy.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Maxime Ripard 2013-07-16 16:45:38 +02:00 committed by Daniel Lezcano
parent a2c49e7b55
commit 7e14183469
1 changed files with 6 additions and 3 deletions
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9
drivers/clocksource/sun4i_timer.c
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@ -38,6 +38,7 @@
#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
static void __iomem *timer_base;
static u32 ticks_per_jiffy;
/*
* When we disable a timer, we need to wait at least for 2 cycles of
@ -74,7 +75,8 @@ static void sun4i_clkevt_time_start(u8 timer, bool periodic)
else
val |= TIMER_CTL_ONESHOT;
writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
timer_base + TIMER_CTL_REG(timer));
}
static void sun4i_clkevt_mode(enum clock_event_mode mode,
@ -83,6 +85,7 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
sun4i_clkevt_time_stop(0);
sun4i_clkevt_time_setup(0, ticks_per_jiffy);
sun4i_clkevt_time_start(0, true);
break;
case CLOCK_EVT_MODE_ONESHOT:
@ -169,9 +172,9 @@ static void __init sun4i_timer_init(struct device_node *node)
clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
rate, 300, 32, clocksource_mmio_readl_down);
writel(rate / HZ, timer_base + TIMER_INTVAL_REG(0));
ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M) | TIMER_CTL_RELOAD,
writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
timer_base + TIMER_CTL_REG(0));
ret = setup_irq(irq, &sun4i_timer_irq);