PCI: Block on access to temporarily unavailable pci device
The existing implementation of pci_block_user_cfg_access() was recently criticised for providing out of date information and for returning errors on write, which applications won't be expecting. This reimplementation uses a global wait queue and a bit per device. I've open-coded prepare_to_wait() / finish_wait() as I could optimise it significantly by knowing that the pci_lock protected us at all points. It looked a bit funny to be doing a spin_unlock_irqsave(); schedule(), so I used spin_lock_irq() for the _user versions of pci_read_config and pci_write_config. Not carrying a flags pointer around made the code much less nasty. Attempts to block an already blocked device hit a BUG() and attempts to unblock an already unblocked device hit a WARN(). If we need to block access to a device from userspace, it's because it's unsafe for even another bit of the kernel to access the device. An attempt to block a device for a second time means we're about to access the device to perform some other operation, which could provoke undefined behaviour from the device. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Acked-by: Adam Belay <abelay@novell.com> Acked-by: Alan Cox <alan@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -1,6 +1,7 @@
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/wait.h>
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#include "pci.h"
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@ -63,30 +64,42 @@ EXPORT_SYMBOL(pci_bus_write_config_byte);
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EXPORT_SYMBOL(pci_bus_write_config_word);
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EXPORT_SYMBOL(pci_bus_write_config_dword);
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static u32 pci_user_cached_config(struct pci_dev *dev, int pos)
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{
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u32 data;
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/*
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* The following routines are to prevent the user from accessing PCI config
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* space when it's unsafe to do so. Some devices require this during BIST and
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* we're required to prevent it during D-state transitions.
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*
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* We have a bit per device to indicate it's blocked and a global wait queue
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* for callers to sleep on until devices are unblocked.
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*/
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static DECLARE_WAIT_QUEUE_HEAD(pci_ucfg_wait);
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data = dev->saved_config_space[pos/sizeof(dev->saved_config_space[0])];
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data >>= (pos % sizeof(dev->saved_config_space[0])) * 8;
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return data;
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static noinline void pci_wait_ucfg(struct pci_dev *dev)
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{
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DECLARE_WAITQUEUE(wait, current);
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__add_wait_queue(&pci_ucfg_wait, &wait);
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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spin_unlock_irq(&pci_lock);
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schedule();
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spin_lock_irq(&pci_lock);
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} while (dev->block_ucfg_access);
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__remove_wait_queue(&pci_ucfg_wait, &wait);
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}
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#define PCI_USER_READ_CONFIG(size,type) \
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int pci_user_read_config_##size \
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(struct pci_dev *dev, int pos, type *val) \
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{ \
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unsigned long flags; \
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int ret = 0; \
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u32 data = -1; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irqsave(&pci_lock, flags); \
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if (likely(!dev->block_ucfg_access)) \
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ret = dev->bus->ops->read(dev->bus, dev->devfn, \
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spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
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ret = dev->bus->ops->read(dev->bus, dev->devfn, \
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pos, sizeof(type), &data); \
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else if (pos < sizeof(dev->saved_config_space)) \
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data = pci_user_cached_config(dev, pos); \
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spin_unlock_irqrestore(&pci_lock, flags); \
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spin_unlock_irq(&pci_lock); \
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*val = (type)data; \
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return ret; \
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}
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@ -95,14 +108,13 @@ int pci_user_read_config_##size \
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int pci_user_write_config_##size \
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(struct pci_dev *dev, int pos, type val) \
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{ \
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unsigned long flags; \
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int ret = -EIO; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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spin_lock_irqsave(&pci_lock, flags); \
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if (likely(!dev->block_ucfg_access)) \
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ret = dev->bus->ops->write(dev->bus, dev->devfn, \
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spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
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ret = dev->bus->ops->write(dev->bus, dev->devfn, \
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pos, sizeof(type), val); \
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spin_unlock_irqrestore(&pci_lock, flags); \
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spin_unlock_irq(&pci_lock); \
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return ret; \
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}
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@ -117,21 +129,23 @@ PCI_USER_WRITE_CONFIG(dword, u32)
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* pci_block_user_cfg_access - Block userspace PCI config reads/writes
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* @dev: pci device struct
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*
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* This function blocks any userspace PCI config accesses from occurring.
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* When blocked, any writes will be bit bucketed and reads will return the
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* data saved using pci_save_state for the first 64 bytes of config
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* space and return 0xff for all other config reads.
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**/
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* When user access is blocked, any reads or writes to config space will
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* sleep until access is unblocked again. We don't allow nesting of
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* block/unblock calls.
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*/
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void pci_block_user_cfg_access(struct pci_dev *dev)
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{
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unsigned long flags;
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int was_blocked;
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pci_save_state(dev);
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/* spinlock to synchronize with anyone reading config space now */
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spin_lock_irqsave(&pci_lock, flags);
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was_blocked = dev->block_ucfg_access;
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dev->block_ucfg_access = 1;
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spin_unlock_irqrestore(&pci_lock, flags);
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/* If we BUG() inside the pci_lock, we're guaranteed to hose
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* the machine */
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BUG_ON(was_blocked);
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}
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EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
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@ -140,14 +154,19 @@ EXPORT_SYMBOL_GPL(pci_block_user_cfg_access);
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* @dev: pci device struct
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*
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* This function allows userspace PCI config accesses to resume.
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**/
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*/
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void pci_unblock_user_cfg_access(struct pci_dev *dev)
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{
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unsigned long flags;
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/* spinlock to synchronize with anyone reading saved config space */
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spin_lock_irqsave(&pci_lock, flags);
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/* This indicates a problem in the caller, but we don't need
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* to kill them, unlike a double-block above. */
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WARN_ON(!dev->block_ucfg_access);
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dev->block_ucfg_access = 0;
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wake_up_all(&pci_ucfg_wait);
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spin_unlock_irqrestore(&pci_lock, flags);
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}
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EXPORT_SYMBOL_GPL(pci_unblock_user_cfg_access);
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