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[ARM] pxa: move DMA registers definitions into <mach/dma.h>

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1. Driver code where pxa_request_dma() is called will most likely
   reference DMA registers as well,  and it is really unnecessary
   to include pxa-regs.h just for this. Move the definitions into
   <mach/dma.h> and make relevant drivers include it instead of
   <mach/pxa-regs.h>.

2. Introduce DMAC_REGS_VIRT as the virtual address base for these
   DMA registers. This allows later processors to re-use the same
   IP while registers may start at different I/O address.

Signed-off-by: Eric Miao <eric.miao@marvell.com>
This commit is contained in:
Eric Miao 2009-01-02 19:38:42 +08:00
parent fef1f99a0c
commit 7ebc8d56f4
10 changed files with 60 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-pxa/dma.c
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@ -23,8 +23,6 @@
#include <mach/hardware.h>
#include <mach/dma.h>
#include <mach/pxa-regs.h>
struct dma_channel {
char *name;
pxa_dma_prio prio;

56
arch/arm/mach-pxa/include/mach/dma.h
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@ -12,6 +12,62 @@
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#include <mach/hardware.h>
/* DMA Controller Registers Definitions */
#define DMAC_REGS_VIRT io_p2v(0x40000000)
#define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
#define DCSR(n) DMAC_REG((n) << 2)
#define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */
#define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */
#define DDADR(n) DMAC_REG(0x0200 + ((n) << 4))
#define DSADR(n) DMAC_REG(0x0204 + ((n) << 4))
#define DTADR(n) DMAC_REG(0x0208 + ((n) << 4))
#define DCMD(n) DMAC_REG(0x020c + ((n) << 4))
#define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
(((n) & 0x3f) << 2))
#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
#define DCSR_EORINTR (1 << 9) /* The end of Receive */
#endif
#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
#define DDADR_STOP (1 << 0) /* Stop (read / write) */
#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
/*
* Descriptor structure for PXA's DMA engine
* Note: this structure must always be aligned to a 16-byte boundary.

59
arch/arm/mach-pxa/include/mach/pxa-regs.h
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@ -65,65 +65,6 @@
#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
/*
* DMA Controller
*/
#define DCSR(x) __REG2(0x40000000, (x) << 2)
#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
#define DCSR_EORINTR (1 << 9) /* The end of Receive */
#endif
#define DALGN __REG(0x400000a0) /* DMA Alignment Register */
#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
#define DRCMR(n) (*(((n) < 64) ? \
&__REG2(0x40000100, ((n) & 0x3f) << 2) : \
&__REG2(0x40001100, ((n) & 0x3f) << 2)))
#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
#define DDADR(x) __REG2(0x40000200, (x) << 4)
#define DSADR(x) __REG2(0x40000204, (x) << 4)
#define DTADR(x) __REG2(0x40000208, (x) << 4)
#define DCMD(x) __REG2(0x4000020c, (x) << 4)
#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
#define DDADR_STOP (1 << 0) /* Stop (read / write) */
#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
/*
* Real Time Clock
*/

1
drivers/media/video/pxa_camera.c
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@ -35,7 +35,6 @@
#include <linux/videodev2.h>
#include <mach/dma.h>
#include <mach/pxa-regs.h>
#include <mach/camera.h>
#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)

3
drivers/mmc/host/pxamci.c
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@ -30,9 +30,8 @@
#include <asm/sizes.h>
#include <mach/dma.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/dma.h>
#include <mach/mmc.h>
#include "pxamci.h"

1
drivers/mtd/nand/pxa3xx_nand.c
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@ -22,7 +22,6 @@
#include <linux/irq.h>
#include <mach/dma.h>
#include <mach/pxa-regs.h>
#include <mach/pxa3xx_nand.h>
#define CHIP_DELAY_TIMEOUT (2 * HZ/10)

2
drivers/spi/pxa2xx_spi.c
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@ -34,8 +34,6 @@
#include <asm/delay.h>
#include <mach/dma.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/regs-ssp.h>
#include <mach/ssp.h>
#include <mach/pxa2xx_spi.h>

2
sound/soc/pxa/pxa-ssp.c
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@ -29,7 +29,7 @@
#include <sound/pxa2xx-lib.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/dma.h>
#include <mach/regs-ssp.h>
#include <mach/audio.h>
#include <mach/ssp.h>

2
sound/soc/pxa/pxa2xx-ac97.c
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@ -20,8 +20,8 @@
#include <sound/pxa2xx-lib.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/regs-ac97.h>
#include <mach/dma.h>
#include "pxa2xx-pcm.h"
#include "pxa2xx-ac97.h"

2
sound/soc/pxa/pxa2xx-i2s.c
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@ -24,7 +24,7 @@
#include <sound/pxa2xx-lib.h>
#include <mach/hardware.h>
#include <mach/pxa-regs.h>
#include <mach/dma.h>
#include <mach/pxa2xx-gpio.h>
#include <mach/audio.h>