[ALSA] oxygen: add 192 kHz SPDIF input support
Change the oxygen_spdif_input_bits_changed() function so that clock changes on the SPDIF input are correctly detected. This means that sample rates greater than 96 kHz are now supported. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
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5a256f862c
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@ -74,7 +74,9 @@ static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
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if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
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spin_lock(&chip->reg_lock);
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i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
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if (i & OXYGEN_SPDIF_RATE_INT) {
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if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
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OXYGEN_SPDIF_RATE_INT)) {
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/* write the interrupt bit(s) to clear */
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oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
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schedule_work(&chip->spdif_input_bits_work);
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}
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@ -94,30 +96,46 @@ static void oxygen_spdif_input_bits_changed(struct work_struct *work)
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{
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struct oxygen *chip = container_of(work, struct oxygen,
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spdif_input_bits_work);
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u32 reg;
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spin_lock_irq(&chip->reg_lock);
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oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_IN_CLOCK_96,
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OXYGEN_SPDIF_IN_CLOCK_MASK);
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spin_unlock_irq(&chip->reg_lock);
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/*
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* This function gets called when there is new activity on the SPDIF
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* input, or when we lose lock on the input signal, or when the rate
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* changes.
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*/
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msleep(1);
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if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
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& OXYGEN_SPDIF_LOCK_STATUS)) {
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spin_lock_irq(&chip->reg_lock);
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oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_IN_CLOCK_192,
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OXYGEN_SPDIF_IN_CLOCK_MASK);
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spin_lock_irq(&chip->reg_lock);
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reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
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if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
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OXYGEN_SPDIF_LOCK_STATUS))
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== OXYGEN_SPDIF_SENSE_STATUS) {
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/*
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* If we detect activity on the SPDIF input but cannot lock to
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* a signal, the clock bit is likely to be wrong.
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*/
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reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
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oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
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spin_unlock_irq(&chip->reg_lock);
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msleep(1);
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if (!(oxygen_read32(chip, OXYGEN_SPDIF_CONTROL)
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& OXYGEN_SPDIF_LOCK_STATUS)) {
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spin_lock_irq(&chip->reg_lock);
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oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_IN_CLOCK_96,
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OXYGEN_SPDIF_IN_CLOCK_MASK);
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spin_unlock_irq(&chip->reg_lock);
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spin_lock_irq(&chip->reg_lock);
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reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
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if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
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OXYGEN_SPDIF_LOCK_STATUS))
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== OXYGEN_SPDIF_SENSE_STATUS) {
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/* nothing detected with either clock; give up */
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if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
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== OXYGEN_SPDIF_IN_CLOCK_192) {
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/*
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* Reset clock to <= 96 kHz because this is
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* more likely to be received next time.
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*/
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reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
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reg |= OXYGEN_SPDIF_IN_CLOCK_96;
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oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
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}
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}
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}
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spin_unlock_irq(&chip->reg_lock);
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if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
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spin_lock_irq(&chip->reg_lock);
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@ -126,6 +144,10 @@ static void oxygen_spdif_input_bits_changed(struct work_struct *work)
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chip->interrupt_mask);
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spin_unlock_irq(&chip->reg_lock);
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/*
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* We don't actually know that any channel status bits have
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* changed, but let's send a notification just to be sure.
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*/
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snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
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&chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
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}
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@ -225,7 +247,20 @@ static void __devinit oxygen_init(struct oxygen *chip)
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OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
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OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
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OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
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oxygen_set_bits32(chip, OXYGEN_SPDIF_CONTROL, OXYGEN_SPDIF_RATE_MASK);
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oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
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OXYGEN_SPDIF_SENSE_MASK |
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OXYGEN_SPDIF_LOCK_MASK |
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OXYGEN_SPDIF_RATE_MASK |
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OXYGEN_SPDIF_LOCK_PAR |
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OXYGEN_SPDIF_IN_CLOCK_96,
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OXYGEN_SPDIF_OUT_ENABLE |
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OXYGEN_SPDIF_LOOPBACK |
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OXYGEN_SPDIF_SENSE_MASK |
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OXYGEN_SPDIF_LOCK_MASK |
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OXYGEN_SPDIF_RATE_MASK |
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OXYGEN_SPDIF_SENSE_PAR |
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OXYGEN_SPDIF_LOCK_PAR |
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OXYGEN_SPDIF_IN_CLOCK_MASK);
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oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
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oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
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OXYGEN_PLAY_MULTICH_I2S_DAC | OXYGEN_PLAY_SPDIF_SPDIF |
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@ -85,12 +85,16 @@ static struct snd_pcm_hardware oxygen_hardware[PCM_COUNT] = {
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SNDRV_PCM_INFO_SYNC_START,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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.rates = SNDRV_PCM_RATE_44100 |
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.rates = SNDRV_PCM_RATE_32000 |
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SNDRV_PCM_RATE_44100 |
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SNDRV_PCM_RATE_48000 |
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SNDRV_PCM_RATE_64000 |
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SNDRV_PCM_RATE_88200 |
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SNDRV_PCM_RATE_96000,
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.rate_min = 44100,
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.rate_max = 96000,
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SNDRV_PCM_RATE_96000 |
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SNDRV_PCM_RATE_176400 |
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SNDRV_PCM_RATE_192000,
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.rate_min = 32000,
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.rate_max = 192000,
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.channels_min = 2,
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.channels_max = 2,
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.buffer_bytes_max = 256 * 1024,
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