[ARM] 2787/2: PXA27x low power modes support
Patch from Todd Poynor Add symbols for PXA2xx PWRMODE register M field that selects low-power mode, replace unadorned constants. Honor power mode parameter of pxa_cpu_suspend(mode), no longer force to 3 (sleep). Full Deep Sleep low-power mode support for PXA27x is pending generic PM interfaces to select more than 2 suspend-to-RAM-style power modes, but this is expected soon. This can be hardcoded in the meantime by replacing the pxa_cpu_suspend() parameter value. From David Burrage and Todd Poynor. Try #2 removes one of the register copies and moves the code to save the pxa_cpu_suspend parameter to immediately surround the call that requires the parameter value be preserved. Signed-off-by: Todd Poynor <tpoynor@mvista.com> Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -129,7 +129,7 @@ void pxa_cpu_pm_enter(suspend_state_t state)
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case PM_SUSPEND_MEM:
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/* set resume return address */
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PSPR = virt_to_phys(pxa_cpu_resume);
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pxa_cpu_suspend(3);
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pxa_cpu_suspend(PWRMODE_SLEEP);
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break;
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}
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}
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@ -157,7 +157,7 @@ void pxa_cpu_pm_enter(suspend_state_t state)
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case PM_SUSPEND_MEM:
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/* set resume return address */
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PSPR = virt_to_phys(pxa_cpu_resume);
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pxa_cpu_suspend(3);
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pxa_cpu_suspend(PWRMODE_SLEEP);
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break;
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}
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}
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@ -28,7 +28,9 @@
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/*
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* pxa_cpu_suspend()
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*
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* Forces CPU into sleep state
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* Forces CPU into sleep state.
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*
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* r0 = value for PWRMODE M field for desired sleep state
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*/
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ENTRY(pxa_cpu_suspend)
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@ -53,6 +55,7 @@ ENTRY(pxa_cpu_suspend)
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mov r10, sp
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stmfd sp!, {r3 - r10}
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mov r5, r0 @ save sleep mode
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@ preserve phys address of stack
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mov r0, sp
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bl sleep_phys_sp
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@ -66,7 +69,7 @@ ENTRY(pxa_cpu_suspend)
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@ (also workaround for sighting 28071)
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@ prepare value for sleep mode
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mov r1, #3 @ sleep mode
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mov r1, r5 @ sleep mode
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@ prepare pointer to physical address 0 (virtual mapping in generic.c)
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mov r2, #UNCACHED_PHYS_0
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@ -21,7 +21,7 @@
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ENTRY(pxa_cpu_standby)
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ldr r0, =PSSR
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mov r1, #(PSSR_PH | PSSR_STS)
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mov r2, #2
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mov r2, #PWRMODE_STANDBY
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mov r3, #UNCACHED_PHYS_0 @ Read mem context in.
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ldr ip, [r3]
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b 1f
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@ -2282,4 +2282,11 @@
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#endif
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/* PWRMODE register M field values */
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#define PWRMODE_IDLE 0x1
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#define PWRMODE_STANDBY 0x2
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#define PWRMODE_SLEEP 0x3
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#define PWRMODE_DEEPSLEEP 0x7
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#endif
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