leds: lp55xx: configure the clock detection
Now LP55xx provides automatic clock detection API, lp55xx_is_extclk_used(). The clock configuration can be done by the driver itself. (a) Concept The default value is set by each driver with clock selection. The internal clock selection bit is updated in case that the external clock is not detected or clock rate is not 32KHz. (b) Change on LP55xx platform data The clock configuration is done automatically, so no need to define 'update_config' in the platform side. Correlated information are removed in the documentations and header. (c) Definitions moved from header to driver files CONFIG register values are moved each driver, LP5521 and LP5562. Not necessary definitions are removed also. Signed-off-by: Milo(Woogyom) Kim <milo.kim@ti.com> Signed-off-by: Bryan Wu <cooloney@gmail.com>
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@ -81,22 +81,3 @@ static struct lp55xx_platform_data lp5521_platform_data = {
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If the current is set to 0 in the platform data, that channel is
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disabled and it is not visible in the sysfs.
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The 'update_config' : CONFIG register (ADDR 08h)
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This value is platform-specific data.
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If update_config is not defined, the CONFIG register is set with
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'LP5521_PWRSAVE_EN | LP5521_CP_MODE_AUTO | LP5521_R_TO_BATT'.
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(Enable auto-powersave, set charge pump to auto, red to battery)
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example of update_config :
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#define LP5521_CONFIGS (LP5521_PWM_HF | LP5521_PWRSAVE_EN | \
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LP5521_CP_MODE_AUTO | LP5521_R_TO_BATT | \
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LP5521_CLK_INT)
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static struct lp55xx_platform_data lp5521_pdata = {
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.led_config = lp5521_led_config,
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.num_channels = ARRAY_SIZE(lp5521_led_config),
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.clock_mode = LP55XX_CLOCK_INT,
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.update_config = LP5521_CONFIGS,
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};
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@ -118,18 +118,3 @@ static struct lp55xx_platform_data lp5562_platform_data = {
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If the current is set to 0 in the platform data, that channel is
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disabled and it is not visible in the sysfs.
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The 'update_config' : CONFIG register (ADDR 08h)
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This value is platform-specific data.
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If update_config is not defined, the CONFIG register is set with
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'LP5562_PWRSAVE_EN | LP5562_CLK_AUTO'.
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(Enable auto-powersave, set automatic clock source selection)
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#define LP5562_CONFIGS (LP5562_PWM_HF | LP5562_PWRSAVE_EN | \
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LP5562_CLK_SRC_EXT)
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static struct lp55xx_platform_data lp5562_pdata = {
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.led_config = lp5562_led_config,
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.num_channels = ARRAY_SIZE(lp5562_led_config),
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.update_config = LP5562_CONFIGS,
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};
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@ -68,6 +68,18 @@
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#define LP5521_ENABLE_RUN_PROGRAM \
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(LP5521_ENABLE_DEFAULT | LP5521_EXEC_RUN)
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/* CONFIG register */
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#define LP5521_PWM_HF 0x40 /* PWM: 0 = 256Hz, 1 = 558Hz */
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#define LP5521_PWRSAVE_EN 0x20 /* 1 = Power save mode */
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#define LP5521_CP_MODE_OFF 0 /* Charge pump (CP) off */
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#define LP5521_CP_MODE_BYPASS 8 /* CP forced to bypass mode */
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#define LP5521_CP_MODE_1X5 0x10 /* CP forced to 1.5x mode */
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#define LP5521_CP_MODE_AUTO 0x18 /* Automatic mode selection */
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#define LP5521_R_TO_BATT 0x04 /* R out: 0 = CP, 1 = Vbat */
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#define LP5521_CLK_INT 0x01 /* Internal clock */
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#define LP5521_DEFAULT_CFG \
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(LP5521_PWM_HF | LP5521_PWRSAVE_EN | LP5521_CP_MODE_AUTO)
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/* Status */
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#define LP5521_EXT_CLK_USED 0x08
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@ -296,8 +308,11 @@ static int lp5521_post_init_device(struct lp55xx_chip *chip)
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/* Set all PWMs to direct control mode */
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ret = lp55xx_write(chip, LP5521_REG_OP_MODE, LP5521_CMD_DIRECT);
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val = chip->pdata->update_config ?
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: (LP5521_PWRSAVE_EN | LP5521_CP_MODE_AUTO | LP5521_R_TO_BATT);
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/* Update configuration for the clock setting */
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val = LP5521_DEFAULT_CFG;
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if (!lp55xx_is_extclk_used(chip))
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val |= LP5521_CLK_INT;
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ret = lp55xx_write(chip, LP5521_REG_CONFIG, val);
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if (ret)
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return ret;
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@ -71,8 +71,10 @@
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/* CONFIG Register 08h */
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#define LP5562_REG_CONFIG 0x08
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#define LP5562_DEFAULT_CFG \
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(LP5562_PWM_HF | LP5562_PWRSAVE_EN | LP5562_CLK_INT)
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#define LP5562_PWM_HF 0x40
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#define LP5562_PWRSAVE_EN 0x20
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#define LP5562_CLK_INT 0x01 /* Internal clock */
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#define LP5562_DEFAULT_CFG (LP5562_PWM_HF | LP5562_PWRSAVE_EN)
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/* RESET Register 0Dh */
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#define LP5562_REG_RESET 0x0D
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@ -280,7 +282,7 @@ static void lp5562_firmware_loaded(struct lp55xx_chip *chip)
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static int lp5562_post_init_device(struct lp55xx_chip *chip)
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{
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int ret;
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u8 update_cfg = chip->pdata->update_config ? : LP5562_DEFAULT_CFG;
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u8 cfg = LP5562_DEFAULT_CFG;
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/* Set all PWMs to direct control mode */
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ret = lp55xx_write(chip, LP5562_REG_OP_MODE, LP5562_CMD_DIRECT);
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@ -289,7 +291,11 @@ static int lp5562_post_init_device(struct lp55xx_chip *chip)
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lp5562_wait_opmode_done();
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ret = lp55xx_write(chip, LP5562_REG_CONFIG, update_cfg);
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/* Update configuration for the clock setting */
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if (!lp55xx_is_extclk_used(chip))
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cfg |= LP5562_CLK_INT;
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ret = lp55xx_write(chip, LP5562_REG_CONFIG, cfg);
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if (ret)
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return ret;
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@ -20,25 +20,6 @@
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#define LP55XX_CLOCK_INT 1
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#define LP55XX_CLOCK_EXT 2
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/* Bits in LP5521 CONFIG register. 'update_config' in lp55xx_platform_data */
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#define LP5521_PWM_HF 0x40 /* PWM: 0 = 256Hz, 1 = 558Hz */
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#define LP5521_PWRSAVE_EN 0x20 /* 1 = Power save mode */
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#define LP5521_CP_MODE_OFF 0 /* Charge pump (CP) off */
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#define LP5521_CP_MODE_BYPASS 8 /* CP forced to bypass mode */
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#define LP5521_CP_MODE_1X5 0x10 /* CP forced to 1.5x mode */
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#define LP5521_CP_MODE_AUTO 0x18 /* Automatic mode selection */
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#define LP5521_R_TO_BATT 4 /* R out: 0 = CP, 1 = Vbat */
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#define LP5521_CLK_SRC_EXT 0 /* Ext-clk source (CLK_32K) */
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#define LP5521_CLK_INT 1 /* Internal clock */
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#define LP5521_CLK_AUTO 2 /* Automatic clock selection */
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/* Bits in LP5562 CONFIG register */
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#define LP5562_PWM_HF LP5521_PWM_HF
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#define LP5562_PWRSAVE_EN LP5521_PWRSAVE_EN
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#define LP5562_CLK_SRC_EXT LP5521_CLK_SRC_EXT
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#define LP5562_CLK_INT LP5521_CLK_INT
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#define LP5562_CLK_AUTO LP5521_CLK_AUTO
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struct lp55xx_led_config {
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const char *name;
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u8 chan_nr;
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@ -86,9 +67,6 @@ struct lp55xx_platform_data {
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/* Predefined pattern data */
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struct lp55xx_predef_pattern *patterns;
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unsigned int num_patterns;
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/* _CONFIG register */
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u8 update_config;
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};
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#endif /* _LEDS_LP55XX_H */
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