Documentation/memory-barriers.txt: various fixes
Fix various grammatical issues in Documentation/memory-barriers.txt. Cc: "Robert P. J. Day" <rpjday@mindspring.com> Signed-off-by: Jarek Poplawski <jarkao2@o2.pl> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Jarek Poplawski
Linus Torvalds
parent
03491c9293
commit
81fc632355
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@ -24,7 +24,7 @@ Contents:
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(*) Explicit kernel barriers.
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- Compiler barrier.
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- The CPU memory barriers.
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- CPU memory barriers.
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- MMIO write barrier.
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(*) Implicit kernel memory barriers.
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@ -265,7 +265,7 @@ Memory barriers are such interventions. They impose a perceived partial
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ordering over the memory operations on either side of the barrier.
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Such enforcement is important because the CPUs and other devices in a system
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can use a variety of tricks to improve performance - including reordering,
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can use a variety of tricks to improve performance, including reordering,
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deferral and combination of memory operations; speculative loads; speculative
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branch prediction and various types of caching. Memory barriers are used to
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override or suppress these tricks, allowing the code to sanely control the
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@ -457,7 +457,7 @@ sequence, Q must be either &A or &B, and that:
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(Q == &A) implies (D == 1)
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(Q == &B) implies (D == 4)
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But! CPU 2's perception of P may be updated _before_ its perception of B, thus
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But! CPU 2's perception of P may be updated _before_ its perception of B, thus
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leading to the following situation:
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(Q == &B) and (D == 2) ????
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@ -573,7 +573,7 @@ Basically, the read barrier always has to be there, even though it can be of
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the "weaker" type.
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[!] Note that the stores before the write barrier would normally be expected to
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match the loads after the read barrier or data dependency barrier, and vice
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match the loads after the read barrier or the data dependency barrier, and vice
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versa:
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CPU 1 CPU 2
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@ -588,7 +588,7 @@ versa:
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EXAMPLES OF MEMORY BARRIER SEQUENCES
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------------------------------------
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Firstly, write barriers act as a partial orderings on store operations.
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Firstly, write barriers act as partial orderings on store operations.
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Consider the following sequence of events:
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CPU 1
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@ -608,15 +608,15 @@ STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
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+-------+ : :
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| | +------+
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| |------>| C=3 | } /\
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| | : +------+ }----- \ -----> Events perceptible
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| | : | A=1 | } \/ to rest of system
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| | : +------+ }----- \ -----> Events perceptible to
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| | : | A=1 | } \/ the rest of the system
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| | : +------+ }
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| CPU 1 | : | B=2 | }
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| | +------+ }
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| | wwwwwwwwwwwwwwww } <--- At this point the write barrier
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| | +------+ } requires all stores prior to the
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| | : | E=5 | } barrier to be committed before
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| | : +------+ } further stores may be take place.
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| | : +------+ } further stores may take place
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| |------>| D=4 | }
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| | +------+
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+-------+ : :
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@ -626,7 +626,7 @@ STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
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V
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Secondly, data dependency barriers act as a partial orderings on data-dependent
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Secondly, data dependency barriers act as partial orderings on data-dependent
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loads. Consider the following sequence of events:
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CPU 1 CPU 2
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@ -975,7 +975,7 @@ compiler from moving the memory accesses either side of it to the other side:
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barrier();
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This a general barrier - lesser varieties of compiler barrier do not exist.
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This is a general barrier - lesser varieties of compiler barrier do not exist.
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The compiler barrier has no direct effect on the CPU, which may then reorder
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things however it wishes.
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@ -997,7 +997,7 @@ The Linux kernel has eight basic CPU memory barriers:
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All CPU memory barriers unconditionally imply compiler barriers.
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SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
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systems because it is assumed that a CPU will be appear to be self-consistent,
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systems because it is assumed that a CPU will appear to be self-consistent,
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and will order overlapping accesses correctly with respect to itself.
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[!] Note that SMP memory barriers _must_ be used to control the ordering of
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@ -1146,9 +1146,9 @@ for each construct. These operations all imply certain barriers:
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Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is
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equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
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[!] Note: one of the consequence of LOCKs and UNLOCKs being only one-way
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barriers is that the effects instructions outside of a critical section may
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seep into the inside of the critical section.
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[!] Note: one of the consequences of LOCKs and UNLOCKs being only one-way
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barriers is that the effects of instructions outside of a critical section
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may seep into the inside of the critical section.
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A LOCK followed by an UNLOCK may not be assumed to be full memory barrier
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because it is possible for an access preceding the LOCK to happen after the
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@ -1239,7 +1239,7 @@ three CPUs; then should the following sequence of events occur:
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UNLOCK M UNLOCK Q
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*D = d; *H = h;
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Then there is no guarantee as to what order CPU #3 will see the accesses to *A
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Then there is no guarantee as to what order CPU 3 will see the accesses to *A
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through *H occur in, other than the constraints imposed by the separate locks
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on the separate CPUs. It might, for example, see:
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@ -1269,12 +1269,12 @@ However, if the following occurs:
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UNLOCK M [2]
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*H = h;
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CPU #3 might see:
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CPU 3 might see:
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*E, LOCK M [1], *C, *B, *A, UNLOCK M [1],
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LOCK M [2], *H, *F, *G, UNLOCK M [2], *D
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But assuming CPU #1 gets the lock first, it won't see any of:
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But assuming CPU 1 gets the lock first, CPU 3 won't see any of:
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*B, *C, *D, *F, *G or *H preceding LOCK M [1]
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*A, *B or *C following UNLOCK M [1]
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@ -1327,12 +1327,12 @@ spinlock, for example:
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mmiowb();
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spin_unlock(Q);
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this will ensure that the two stores issued on CPU #1 appear at the PCI bridge
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before either of the stores issued on CPU #2.
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this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
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before either of the stores issued on CPU 2.
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Furthermore, following a store by a load to the same device obviates the need
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for an mmiowb(), because the load forces the store to complete before the load
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Furthermore, following a store by a load from the same device obviates the need
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for the mmiowb(), because the load forces the store to complete before the load
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is performed:
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CPU 1 CPU 2
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@ -1363,7 +1363,7 @@ circumstances in which reordering definitely _could_ be a problem:
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(*) Atomic operations.
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(*) Accessing devices (I/O).
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(*) Accessing devices.
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(*) Interrupts.
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@ -1399,7 +1399,7 @@ To wake up a particular waiter, the up_read() or up_write() functions have to:
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(1) read the next pointer from this waiter's record to know as to where the
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next waiter record is;
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(4) read the pointer to the waiter's task structure;
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(2) read the pointer to the waiter's task structure;
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(3) clear the task pointer to tell the waiter it has been given the semaphore;
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@ -1407,7 +1407,7 @@ To wake up a particular waiter, the up_read() or up_write() functions have to:
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(5) release the reference held on the waiter's task struct.
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In otherwords, it has to perform this sequence of events:
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In other words, it has to perform this sequence of events:
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LOAD waiter->list.next;
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LOAD waiter->task;
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@ -1502,7 +1502,7 @@ operations and adjusting reference counters towards object destruction, and as
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such the implicit memory barrier effects are necessary.
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The following operation are potential problems as they do _not_ imply memory
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The following operations are potential problems as they do _not_ imply memory
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barriers, but might be used for implementing such things as UNLOCK-class
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operations:
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@ -1517,7 +1517,7 @@ With these the appropriate explicit memory barrier should be used if necessary
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The following also do _not_ imply memory barriers, and so may require explicit
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memory barriers under some circumstances (smp_mb__before_atomic_dec() for
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instance)):
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instance):
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atomic_add();
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atomic_sub();
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@ -1641,8 +1641,8 @@ functions:
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indeed have special I/O space access cycles and instructions, but many
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CPUs don't have such a concept.
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The PCI bus, amongst others, defines an I/O space concept - which on such
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CPUs as i386 and x86_64 cpus readily maps to the CPU's concept of I/O
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The PCI bus, amongst others, defines an I/O space concept which - on such
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CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
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space. However, it may also be mapped as a virtual I/O space in the CPU's
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memory map, particularly on those CPUs that don't support alternate I/O
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spaces.
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@ -1664,7 +1664,7 @@ functions:
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i386 architecture machines, for example, this is controlled by way of the
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MTRR registers.
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Ordinarily, these will be guaranteed to be fully ordered and uncombined,,
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Ordinarily, these will be guaranteed to be fully ordered and uncombined,
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provided they're not accessing a prefetchable device.
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However, intermediary hardware (such as a PCI bridge) may indulge in
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@ -1689,7 +1689,7 @@ functions:
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(*) ioreadX(), iowriteX()
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These will perform as appropriate for the type of access they're actually
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These will perform appropriately for the type of access they're actually
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doing, be it inX()/outX() or readX()/writeX().
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@ -1705,7 +1705,7 @@ of arch-specific code.
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This means that it must be considered that the CPU will execute its instruction
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stream in any order it feels like - or even in parallel - provided that if an
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instruction in the stream depends on the an earlier instruction, then that
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instruction in the stream depends on an earlier instruction, then that
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earlier instruction must be sufficiently complete[*] before the later
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instruction may proceed; in other words: provided that the appearance of
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causality is maintained.
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@ -1795,8 +1795,8 @@ eventually become visible on all CPUs, there's no guarantee that they will
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become apparent in the same order on those other CPUs.
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Consider dealing with a system that has pair of CPUs (1 & 2), each of which has
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a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
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Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
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has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
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:
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: +--------+
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@ -1835,7 +1835,7 @@ Imagine the system has the following properties:
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(*) the coherency queue is not flushed by normal loads to lines already
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present in the cache, even though the contents of the queue may
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potentially effect those loads.
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potentially affect those loads.
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Imagine, then, that two writes are made on the first CPU, with a write barrier
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between them to guarantee that they will appear to reach that CPU's caches in
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@ -1845,7 +1845,7 @@ the requisite order:
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=============== =============== =======================================
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u == 0, v == 1 and p == &u, q == &u
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v = 2;
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smp_wmb(); Make sure change to v visible before
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smp_wmb(); Make sure change to v is visible before
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change to p
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<A:modify v=2> v is now in cache A exclusively
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p = &v;
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@ -1853,7 +1853,7 @@ the requisite order:
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The write memory barrier forces the other CPUs in the system to perceive that
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the local CPU's caches have apparently been updated in the correct order. But
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now imagine that the second CPU that wants to read those values:
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now imagine that the second CPU wants to read those values:
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CPU 1 CPU 2 COMMENT
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=============== =============== =======================================
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@ -1861,7 +1861,7 @@ now imagine that the second CPU that wants to read those values:
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q = p;
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x = *q;
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The above pair of reads may then fail to happen in expected order, as the
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The above pair of reads may then fail to happen in the expected order, as the
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cacheline holding p may get updated in one of the second CPU's caches whilst
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the update to the cacheline holding v is delayed in the other of the second
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CPU's caches by some other cache event:
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@ -1916,7 +1916,7 @@ access depends on a read, not all do, so it may not be relied on.
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Other CPUs may also have split caches, but must coordinate between the various
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cachelets for normal memory accesses. The semantics of the Alpha removes the
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need for coordination in absence of memory barriers.
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need for coordination in the absence of memory barriers.
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CACHE COHERENCY VS DMA
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@ -1931,10 +1931,10 @@ invalidate them as well).
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In addition, the data DMA'd to RAM by a device may be overwritten by dirty
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cache lines being written back to RAM from a CPU's cache after the device has
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installed its own data, or cache lines simply present in a CPUs cache may
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simply obscure the fact that RAM has been updated, until at such time as the
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cacheline is discarded from the CPU's cache and reloaded. To deal with this,
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the appropriate part of the kernel must invalidate the overlapping bits of the
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installed its own data, or cache lines present in the CPU's cache may simply
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obscure the fact that RAM has been updated, until at such time as the cacheline
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is discarded from the CPU's cache and reloaded. To deal with this, the
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appropriate part of the kernel must invalidate the overlapping bits of the
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cache on each CPU.
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See Documentation/cachetlb.txt for more information on cache management.
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@ -1944,7 +1944,7 @@ CACHE COHERENCY VS MMIO
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-----------------------
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Memory mapped I/O usually takes place through memory locations that are part of
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a window in the CPU's memory space that have different properties assigned than
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a window in the CPU's memory space that has different properties assigned than
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the usual RAM directed window.
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Amongst these properties is usually the fact that such accesses bypass the
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@ -1960,7 +1960,7 @@ THE THINGS CPUS GET UP TO
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=========================
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A programmer might take it for granted that the CPU will perform memory
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operations in exactly the order specified, so that if a CPU is, for example,
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operations in exactly the order specified, so that if the CPU is, for example,
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given the following piece of code to execute:
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a = *A;
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@ -1969,7 +1969,7 @@ given the following piece of code to execute:
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d = *D;
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*E = e;
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They would then expect that the CPU will complete the memory operation for each
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they would then expect that the CPU will complete the memory operation for each
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instruction before moving on to the next one, leading to a definite sequence of
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operations as seen by external observers in the system:
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@ -1986,8 +1986,8 @@ assumption doesn't hold because:
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(*) loads may be done speculatively, and the result discarded should it prove
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to have been unnecessary;
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(*) loads may be done speculatively, leading to the result having being
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fetched at the wrong time in the expected sequence of events;
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(*) loads may be done speculatively, leading to the result having been fetched
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at the wrong time in the expected sequence of events;
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(*) the order of the memory accesses may be rearranged to promote better use
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of the CPU buses and caches;
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@ -2069,12 +2069,12 @@ AND THEN THERE'S THE ALPHA
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The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
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some versions of the Alpha CPU have a split data cache, permitting them to have
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two semantically related cache lines updating at separate times. This is where
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two semantically-related cache lines updated at separate times. This is where
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the data dependency barrier really becomes necessary as this synchronises both
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caches with the memory coherence system, thus making it seem like pointer
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changes vs new data occur in the right order.
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The Alpha defines the Linux's kernel's memory barrier model.
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The Alpha defines the Linux kernel's memory barrier model.
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See the subsection on "Cache Coherency" above.
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