[SPARC64]: Add missing memory barriers to instruction patching functions.
V9 requires a write memory barrier before the instruction flush. Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -529,15 +529,19 @@ static void __init per_cpu_patch(void)
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};
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*(unsigned int *) (addr + 0) = insns[0];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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*(unsigned int *) (addr + 4) = insns[1];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 4));
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*(unsigned int *) (addr + 8) = insns[2];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 8));
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*(unsigned int *) (addr + 12) = insns[3];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 12));
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p++;
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@ -558,6 +562,7 @@ static void __init gl_patch(void)
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unsigned long addr = p1->addr;
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*(unsigned int *) (addr + 0) = p1->insn;
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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p1++;
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@ -568,9 +573,11 @@ static void __init gl_patch(void)
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unsigned long addr = p2->addr;
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*(unsigned int *) (addr + 0) = p2->insns[0];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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*(unsigned int *) (addr + 3) = p2->insns[1];
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wmb();
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__asm__ __volatile__("flush %0" : : "r" (addr + 4));
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p2++;
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