soc/qman: export non-programmable FQD fields query
Export qman_query_fq_np() function and related structures. This will be needed in the caam/qi driver, where "queue empty" condition will be decided based on the frm_cnt. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -2019,8 +2019,7 @@ int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
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return ret;
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}
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static int qman_query_fq_np(struct qman_fq *fq,
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struct qm_mcr_queryfq_np *np)
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int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
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{
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union qm_mc_command *mcc;
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union qm_mc_result *mcr;
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@ -2046,6 +2045,7 @@ static int qman_query_fq_np(struct qman_fq *fq,
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put_affine_portal();
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return ret;
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}
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EXPORT_SYMBOL(qman_query_fq_np);
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static int qman_query_cgr(struct qman_cgr *cgr,
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struct qm_mcr_querycgr *cgrd)
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@ -89,67 +89,6 @@ static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q)
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return ((u64)q->a_bcnt_hi << 32) | be32_to_cpu(q->a_bcnt_lo);
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}
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/* "Query FQ Non-Programmable Fields" */
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struct qm_mcr_queryfq_np {
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u8 verb;
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u8 result;
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u8 __reserved1;
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u8 state; /* QM_MCR_NP_STATE_*** */
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u32 fqd_link; /* 24-bit, _res2[24-31] */
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u16 odp_seq; /* 14-bit, _res3[14-15] */
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u16 orp_nesn; /* 14-bit, _res4[14-15] */
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u16 orp_ea_hseq; /* 15-bit, _res5[15] */
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u16 orp_ea_tseq; /* 15-bit, _res6[15] */
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u32 orp_ea_hptr; /* 24-bit, _res7[24-31] */
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u32 orp_ea_tptr; /* 24-bit, _res8[24-31] */
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u32 pfdr_hptr; /* 24-bit, _res9[24-31] */
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u32 pfdr_tptr; /* 24-bit, _res10[24-31] */
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u8 __reserved2[5];
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u8 is; /* 1-bit, _res12[1-7] */
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u16 ics_surp;
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u32 byte_cnt;
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u32 frm_cnt; /* 24-bit, _res13[24-31] */
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u32 __reserved3;
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u16 ra1_sfdr; /* QM_MCR_NP_RA1_*** */
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u16 ra2_sfdr; /* QM_MCR_NP_RA2_*** */
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u16 __reserved4;
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u16 od1_sfdr; /* QM_MCR_NP_OD1_*** */
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u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */
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u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */
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} __packed;
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#define QM_MCR_NP_STATE_FE 0x10
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#define QM_MCR_NP_STATE_R 0x08
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#define QM_MCR_NP_STATE_MASK 0x07 /* Reads FQD::STATE; */
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#define QM_MCR_NP_STATE_OOS 0x00
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#define QM_MCR_NP_STATE_RETIRED 0x01
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#define QM_MCR_NP_STATE_TEN_SCHED 0x02
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#define QM_MCR_NP_STATE_TRU_SCHED 0x03
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#define QM_MCR_NP_STATE_PARKED 0x04
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#define QM_MCR_NP_STATE_ACTIVE 0x05
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#define QM_MCR_NP_PTR_MASK 0x07ff /* for RA[12] & OD[123] */
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#define QM_MCR_NP_RA1_NRA(v) (((v) >> 14) & 0x3) /* FQD::NRA */
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#define QM_MCR_NP_RA2_IT(v) (((v) >> 14) & 0x1) /* FQD::IT */
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#define QM_MCR_NP_OD1_NOD(v) (((v) >> 14) & 0x3) /* FQD::NOD */
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#define QM_MCR_NP_OD3_NPC(v) (((v) >> 14) & 0x3) /* FQD::NPC */
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enum qm_mcr_queryfq_np_masks {
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qm_mcr_fqd_link_mask = BIT(24)-1,
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qm_mcr_odp_seq_mask = BIT(14)-1,
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qm_mcr_orp_nesn_mask = BIT(14)-1,
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qm_mcr_orp_ea_hseq_mask = BIT(15)-1,
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qm_mcr_orp_ea_tseq_mask = BIT(15)-1,
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qm_mcr_orp_ea_hptr_mask = BIT(24)-1,
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qm_mcr_orp_ea_tptr_mask = BIT(24)-1,
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qm_mcr_pfdr_hptr_mask = BIT(24)-1,
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qm_mcr_pfdr_tptr_mask = BIT(24)-1,
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qm_mcr_is_mask = BIT(1)-1,
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qm_mcr_frm_cnt_mask = BIT(24)-1,
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};
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#define qm_mcr_np_get(np, field) \
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((np)->field & (qm_mcr_##field##_mask))
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/* Congestion Groups */
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/*
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@ -811,6 +811,67 @@ struct qman_cgr {
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#define QMAN_VOLATILE_FLAG_WAIT_INT 0x00000002 /* if wait, interruptible? */
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#define QMAN_VOLATILE_FLAG_FINISH 0x00000004 /* wait till VDQCR completes */
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/* "Query FQ Non-Programmable Fields" */
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struct qm_mcr_queryfq_np {
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u8 verb;
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u8 result;
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u8 __reserved1;
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u8 state; /* QM_MCR_NP_STATE_*** */
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u32 fqd_link; /* 24-bit, _res2[24-31] */
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u16 odp_seq; /* 14-bit, _res3[14-15] */
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u16 orp_nesn; /* 14-bit, _res4[14-15] */
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u16 orp_ea_hseq; /* 15-bit, _res5[15] */
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u16 orp_ea_tseq; /* 15-bit, _res6[15] */
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u32 orp_ea_hptr; /* 24-bit, _res7[24-31] */
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u32 orp_ea_tptr; /* 24-bit, _res8[24-31] */
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u32 pfdr_hptr; /* 24-bit, _res9[24-31] */
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u32 pfdr_tptr; /* 24-bit, _res10[24-31] */
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u8 __reserved2[5];
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u8 is; /* 1-bit, _res12[1-7] */
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u16 ics_surp;
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u32 byte_cnt;
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u32 frm_cnt; /* 24-bit, _res13[24-31] */
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u32 __reserved3;
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u16 ra1_sfdr; /* QM_MCR_NP_RA1_*** */
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u16 ra2_sfdr; /* QM_MCR_NP_RA2_*** */
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u16 __reserved4;
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u16 od1_sfdr; /* QM_MCR_NP_OD1_*** */
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u16 od2_sfdr; /* QM_MCR_NP_OD2_*** */
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u16 od3_sfdr; /* QM_MCR_NP_OD3_*** */
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} __packed;
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#define QM_MCR_NP_STATE_FE 0x10
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#define QM_MCR_NP_STATE_R 0x08
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#define QM_MCR_NP_STATE_MASK 0x07 /* Reads FQD::STATE; */
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#define QM_MCR_NP_STATE_OOS 0x00
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#define QM_MCR_NP_STATE_RETIRED 0x01
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#define QM_MCR_NP_STATE_TEN_SCHED 0x02
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#define QM_MCR_NP_STATE_TRU_SCHED 0x03
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#define QM_MCR_NP_STATE_PARKED 0x04
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#define QM_MCR_NP_STATE_ACTIVE 0x05
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#define QM_MCR_NP_PTR_MASK 0x07ff /* for RA[12] & OD[123] */
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#define QM_MCR_NP_RA1_NRA(v) (((v) >> 14) & 0x3) /* FQD::NRA */
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#define QM_MCR_NP_RA2_IT(v) (((v) >> 14) & 0x1) /* FQD::IT */
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#define QM_MCR_NP_OD1_NOD(v) (((v) >> 14) & 0x3) /* FQD::NOD */
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#define QM_MCR_NP_OD3_NPC(v) (((v) >> 14) & 0x3) /* FQD::NPC */
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enum qm_mcr_queryfq_np_masks {
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qm_mcr_fqd_link_mask = BIT(24) - 1,
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qm_mcr_odp_seq_mask = BIT(14) - 1,
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qm_mcr_orp_nesn_mask = BIT(14) - 1,
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qm_mcr_orp_ea_hseq_mask = BIT(15) - 1,
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qm_mcr_orp_ea_tseq_mask = BIT(15) - 1,
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qm_mcr_orp_ea_hptr_mask = BIT(24) - 1,
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qm_mcr_orp_ea_tptr_mask = BIT(24) - 1,
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qm_mcr_pfdr_hptr_mask = BIT(24) - 1,
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qm_mcr_pfdr_tptr_mask = BIT(24) - 1,
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qm_mcr_is_mask = BIT(1) - 1,
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qm_mcr_frm_cnt_mask = BIT(24) - 1,
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};
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#define qm_mcr_np_get(np, field) \
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((np)->field & (qm_mcr_##field##_mask))
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/* Portal Management */
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/**
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* qman_p_irqsource_add - add processing sources to be interrupt-driven
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@ -1033,6 +1094,13 @@ int qman_alloc_fqid_range(u32 *result, u32 count);
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*/
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int qman_release_fqid(u32 fqid);
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/**
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* qman_query_fq_np - Queries non-programmable FQD fields
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* @fq: the frame queue object to be queried
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* @np: storage for the queried FQD fields
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*/
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int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np);
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/* Pool-channel management */
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/**
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* qman_alloc_pool_range - Allocate a contiguous range of pool-channel IDs
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