cxgb4: Add pci reset handler
This patch implements reset_prepare and reset_done, which are used for handling FLR. Signed-off-by: Vishal Kulkarni <vishal@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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7b3a768b2b
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86e8f29887
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@ -184,6 +184,8 @@ static struct dentry *cxgb4_debugfs_root;
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LIST_HEAD(adapter_list);
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DEFINE_MUTEX(uld_mutex);
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static int cfg_queues(struct adapter *adap);
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static void link_report(struct net_device *dev)
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{
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if (!netif_carrier_ok(dev))
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@ -4286,14 +4288,14 @@ static struct fw_info *find_fw_info(int chip)
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/*
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* Phase 0 of initialization: contact FW, obtain config, perform basic init.
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*/
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static int adap_init0(struct adapter *adap)
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static int adap_init0(struct adapter *adap, int vpd_skip)
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{
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int ret;
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u32 v, port_vec;
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enum dev_state state;
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u32 params[7], val[7];
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struct fw_caps_config_cmd caps_cmd;
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u32 params[7], val[7];
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enum dev_state state;
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u32 v, port_vec;
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int reset = 1;
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int ret;
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/* Grab Firmware Device Log parameters as early as possible so we have
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* access to it for debugging, etc.
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@ -4448,9 +4450,11 @@ static int adap_init0(struct adapter *adap)
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* could have FLASHed a new VPD which won't be read by the firmware
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* until we do the RESET ...
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*/
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ret = t4_get_vpd_params(adap, &adap->params.vpd);
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if (ret < 0)
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goto bye;
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if (!vpd_skip) {
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ret = t4_get_vpd_params(adap, &adap->params.vpd);
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if (ret < 0)
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goto bye;
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}
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/* Find out what ports are available to us. Note that we need to do
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* this before calling adap_init0_no_config() since it needs nports
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@ -5050,10 +5054,93 @@ static void eeh_resume(struct pci_dev *pdev)
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rtnl_unlock();
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}
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static void eeh_reset_prepare(struct pci_dev *pdev)
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{
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struct adapter *adapter = pci_get_drvdata(pdev);
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int i;
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if (adapter->pf != 4)
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return;
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adapter->flags &= ~CXGB4_FW_OK;
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notify_ulds(adapter, CXGB4_STATE_DOWN);
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for_each_port(adapter, i)
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if (adapter->port[i]->reg_state == NETREG_REGISTERED)
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cxgb_close(adapter->port[i]);
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disable_interrupts(adapter);
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cxgb4_free_mps_ref_entries(adapter);
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adap_free_hma_mem(adapter);
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if (adapter->flags & CXGB4_FULL_INIT_DONE)
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cxgb_down(adapter);
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}
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static void eeh_reset_done(struct pci_dev *pdev)
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{
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struct adapter *adapter = pci_get_drvdata(pdev);
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int err, i;
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if (adapter->pf != 4)
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return;
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err = t4_wait_dev_ready(adapter->regs);
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if (err < 0) {
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dev_err(adapter->pdev_dev,
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"Device not ready, err %d", err);
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return;
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}
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setup_memwin(adapter);
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err = adap_init0(adapter, 1);
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if (err) {
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dev_err(adapter->pdev_dev,
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"Adapter init failed, err %d", err);
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return;
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}
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setup_memwin_rdma(adapter);
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if (adapter->flags & CXGB4_FW_OK) {
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err = t4_port_init(adapter, adapter->pf, adapter->pf, 0);
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if (err) {
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dev_err(adapter->pdev_dev,
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"Port init failed, err %d", err);
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return;
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}
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}
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err = cfg_queues(adapter);
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if (err) {
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dev_err(adapter->pdev_dev,
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"Config queues failed, err %d", err);
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return;
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}
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cxgb4_init_mps_ref_entries(adapter);
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err = setup_fw_sge_queues(adapter);
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if (err) {
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dev_err(adapter->pdev_dev,
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"FW sge queue allocation failed, err %d", err);
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return;
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}
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for_each_port(adapter, i)
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if (adapter->port[i]->reg_state == NETREG_REGISTERED)
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cxgb_open(adapter->port[i]);
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}
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static const struct pci_error_handlers cxgb4_eeh = {
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.error_detected = eeh_err_detected,
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.slot_reset = eeh_slot_reset,
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.resume = eeh_resume,
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.reset_prepare = eeh_reset_prepare,
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.reset_done = eeh_reset_done,
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};
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/* Return true if the Link Configuration supports "High Speeds" (those greater
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@ -5837,7 +5924,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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}
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setup_memwin(adapter);
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err = adap_init0(adapter);
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err = adap_init0(adapter, 0);
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#ifdef CONFIG_DEBUG_FS
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bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
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#endif
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