luck/tmp_suning_uos_patched
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

CLK: Pistachio: Register system interface gate clocks

Browse Source 
Register the system interface gate clocks provided by the peripheral
general control block.  These clocks gate register access for various
peripherals.

Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Patchwork: https://patchwork.linux-mips.org/patch/9322/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Andrew Bresticker 2015-02-24 19:56:06 -08:00 committed by Ralf Baechle
parent 44960ab862
commit 8cb94af684
1 changed files with 42 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
drivers/clk/pistachio/clk-pistachio.c
View File

@ -264,3 +264,45 @@ static void __init pistachio_clk_periph_init(struct device_node *np)
}
CLK_OF_DECLARE(pistachio_clk_periph, "img,pistachio-clk-periph",
pistachio_clk_periph_init);
static struct pistachio_gate pistachio_sys_gates[] __initdata = {
GATE(SYS_CLK_I2C0, "i2c0_sys", "sys", 0x8, 0),
GATE(SYS_CLK_I2C1, "i2c1_sys", "sys", 0x8, 1),
GATE(SYS_CLK_I2C2, "i2c2_sys", "sys", 0x8, 2),
GATE(SYS_CLK_I2C3, "i2c3_sys", "sys", 0x8, 3),
GATE(SYS_CLK_I2S_IN, "i2s_in_sys", "sys", 0x8, 4),
GATE(SYS_CLK_PAUD_OUT, "paud_out_sys", "sys", 0x8, 5),
GATE(SYS_CLK_SPDIF_OUT, "spdif_out_sys", "sys", 0x8, 6),
GATE(SYS_CLK_SPI0_MASTER, "spi0_master_sys", "sys", 0x8, 7),
GATE(SYS_CLK_SPI0_SLAVE, "spi0_slave_sys", "sys", 0x8, 8),
GATE(SYS_CLK_PWM, "pwm_sys", "sys", 0x8, 9),
GATE(SYS_CLK_UART0, "uart0_sys", "sys", 0x8, 10),
GATE(SYS_CLK_UART1, "uart1_sys", "sys", 0x8, 11),
GATE(SYS_CLK_SPI1, "spi1_sys", "sys", 0x8, 12),
GATE(SYS_CLK_MDC, "mdc_sys", "sys", 0x8, 13),
GATE(SYS_CLK_SD_HOST, "sd_host_sys", "sys", 0x8, 14),
GATE(SYS_CLK_ENET, "enet_sys", "sys", 0x8, 15),
GATE(SYS_CLK_IR, "ir_sys", "sys", 0x8, 16),
GATE(SYS_CLK_WD, "wd_sys", "sys", 0x8, 17),
GATE(SYS_CLK_TIMER, "timer_sys", "sys", 0x8, 18),
GATE(SYS_CLK_I2S_OUT, "i2s_out_sys", "sys", 0x8, 24),
GATE(SYS_CLK_SPDIF_IN, "spdif_in_sys", "sys", 0x8, 25),
GATE(SYS_CLK_EVENT_TIMER, "event_timer_sys", "sys", 0x8, 26),
GATE(SYS_CLK_HASH, "hash_sys", "sys", 0x8, 27),
};
static void __init pistachio_cr_periph_init(struct device_node *np)
{
struct pistachio_clk_provider *p;
p = pistachio_clk_alloc_provider(np, SYS_CLK_NR_CLKS);
if (!p)
return;
pistachio_clk_register_gate(p, pistachio_sys_gates,
ARRAY_SIZE(pistachio_sys_gates));
pistachio_clk_register_provider(p);
}
CLK_OF_DECLARE(pistachio_cr_periph, "img,pistachio-cr-periph",
pistachio_cr_periph_init);