ide: use only ->set_pio_mode method for programming PIO modes (take 2)
Use ->set_pio_mode method to program PIO modes in ide_set_xfer_rate() (the only place which used ->speedproc to program PIO modes) and remove handling of PIO modes from all ->speedproc implementations. v2: * Fix pmac_ide_tune_chipset() comment. There should be no functionality changes caused by this patch. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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@ -724,11 +724,6 @@ static int speed_cris_ide(ide_drive_t *drive, const u8 speed)
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{
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int cyc = 0, dvs = 0, strobe = 0, hold = 0;
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if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
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cris_set_pio_mode(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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}
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switch(speed)
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{
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case XFER_UDMA_0:
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@ -398,6 +398,18 @@ int ide_set_xfer_rate(ide_drive_t *drive, u8 rate)
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rate = ide_rate_filter(drive, rate);
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if (rate >= XFER_PIO_0 && rate <= XFER_PIO_5) {
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if (hwif->set_pio_mode)
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hwif->set_pio_mode(drive, rate - XFER_PIO_0);
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/*
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* FIXME: this is incorrect to return zero here but
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* since all users of ide_set_xfer_rate() ignore
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* the return value it is not a problem currently
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*/
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return 0;
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}
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return hwif->speedproc(drive, rate);
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}
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@ -177,11 +177,6 @@ static int auide_tune_chipset(ide_drive_t *drive, const u8 speed)
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mem_sttime = 0;
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mem_stcfg = au_readl(MEM_STCFG2);
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if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
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au1xxx_set_pio_mode(drive, speed - XFER_PIO_0);
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return 0;
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}
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switch(speed) {
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#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
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case XFER_MW_DMA_2:
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@ -421,11 +421,6 @@ static int ali15x3_tune_chipset(ide_drive_t *drive, const u8 speed)
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if (speed < XFER_PIO_0)
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return 1;
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if (speed >= XFER_PIO_0 && speed <= XFER_PIO_5) {
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ali_tune_pio(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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}
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if (speed == XFER_UDMA_6)
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speed1 = 0x47;
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@ -178,11 +178,6 @@ static int atiixp_speedproc(ide_drive_t *drive, const u8 speed)
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u16 tmp16;
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u8 pio;
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if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
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atiixp_tune_pio(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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}
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spin_lock_irqsave(&atiixp_lock, flags);
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save_mdma_mode[drive->dn] = 0;
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@ -323,14 +323,6 @@ static int cmd64x_tune_chipset(ide_drive_t *drive, const u8 speed)
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case XFER_MW_DMA_0:
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program_cycle_times(drive, 480, 215);
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break;
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case XFER_PIO_5:
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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cmd64x_tune_pio(drive, speed - XFER_PIO_0);
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break;
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default:
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return 1;
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}
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@ -66,30 +66,13 @@ static struct pio_clocks cs5520_pio_clocks[]={
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{1, 2, 1}
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};
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static int cs5520_tune_chipset(ide_drive_t *drive, const u8 speed)
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static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *pdev = hwif->pci_dev;
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int pio = speed;
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u8 reg;
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int controller = drive->dn > 1 ? 1 : 0;
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u8 reg;
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switch(speed)
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{
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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pio -= XFER_PIO_0;
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break;
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default:
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pio = 0;
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printk(KERN_ERR "cs55x0: bad ide timing.\n");
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}
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printk("PIO clocking = %d\n", pio);
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/* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
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/* 8bit CAT/CRT - 8bit command timing for channel */
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@ -114,12 +97,21 @@ static int cs5520_tune_chipset(ide_drive_t *drive, const u8 speed)
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reg |= 1<<((drive->dn&1)+5);
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outb(reg, hwif->dma_base + 0x02 + 8*controller);
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return ide_config_drive_speed(drive, speed);
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(void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
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}
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static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
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static int cs5520_tune_chipset(ide_drive_t *drive, const u8 speed)
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{
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cs5520_tune_chipset(drive, XFER_PIO_0 + pio);
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printk(KERN_ERR "cs55x0: bad ide timing.\n");
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cs5520_set_pio_mode(drive, 0);
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/*
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* FIXME: this is incorrect to return zero here but
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* since all users of ide_set_xfer_rate() ignore
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* the return value it is not a problem currently
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*/
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return 0;
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}
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static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
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@ -163,13 +163,6 @@ static int cs5530_tune_chipset(ide_drive_t *drive, const u8 mode)
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case XFER_MW_DMA_0: timings = 0x00077771; break;
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case XFER_MW_DMA_1: timings = 0x00012121; break;
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case XFER_MW_DMA_2: timings = 0x00002020; break;
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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cs5530_tunepio(drive, mode - XFER_PIO_0);
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return 0;
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default:
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BUG();
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break;
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@ -132,11 +132,6 @@ static int it8213_tune_chipset(ide_drive_t *drive, const u8 speed)
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u16 reg4042, reg4a;
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u8 reg48, reg54, reg55;
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if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
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it8213_tune_pio(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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}
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pci_read_config_word(dev, maslave, ®4042);
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pci_read_config_byte(dev, 0x48, ®48);
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pci_read_config_word(dev, 0x4a, ®4a);
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@ -418,15 +418,6 @@ static int it821x_tune_chipset(ide_drive_t *drive, const u8 speed)
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ide_hwif_t *hwif = drive->hwif;
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struct it821x_dev *itdev = ide_get_hwifdata(hwif);
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switch (speed) {
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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return it821x_tunepio(drive, speed - XFER_PIO_0);
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}
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if (itdev->smart == 0) {
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switch (speed) {
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/* MWDMA tuning is really hard because our MWDMA and PIO
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@ -242,11 +242,6 @@ static int piix_tune_chipset(ide_drive_t *drive, const u8 speed)
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u16 reg4042, reg4a;
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u8 reg48, reg54, reg55;
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if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
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piix_tune_pio(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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}
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pci_read_config_word(dev, maslave, ®4042);
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sitre = (reg4042 & 0x4000) ? 1 : 0;
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pci_read_config_byte(dev, 0x48, ®48);
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@ -152,16 +152,6 @@ static int sc1200_tune_chipset(ide_drive_t *drive, const u8 mode)
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if (sc1200_set_xfer_mode(drive, mode))
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return 1; /* failure */
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switch (mode) {
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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sc1200_tunepio(drive, mode - XFER_PIO_0);
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return 0;
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}
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pci_clock = sc1200_get_pci_clock();
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/*
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case XFER_UDMA_0:
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idx = speed - XFER_UDMA_0;
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break;
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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scc_tune_pio(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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default:
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return 1;
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}
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@ -157,11 +157,6 @@ static int svwks_tune_chipset(ide_drive_t *drive, const u8 speed)
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u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
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if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
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svwks_tune_pio(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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}
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/* If we are about to put a disk into UDMA mode we screwed up.
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Our code assumes we never _ever_ do this on an OSB4 */
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@ -284,13 +284,6 @@ static int siimage_tune_chipset(ide_drive_t *drive, const u8 speed)
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scsc = is_sata(hwif) ? 1 : scsc;
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switch(speed) {
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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sil_tune_pio(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_MW_DMA_0:
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@ -519,15 +519,10 @@ static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
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}
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}
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static int sis5513_tune_drive(ide_drive_t *drive, const u8 pio)
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{
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config_art_rwp_pio(drive, pio);
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return ide_config_drive_speed(drive, XFER_PIO_0 + pio);
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}
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static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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(void)sis5513_tune_drive(drive, pio);
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config_art_rwp_pio(drive, pio);
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(void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
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}
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static int sis5513_tune_chipset(ide_drive_t *drive, const u8 speed)
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@ -537,9 +532,6 @@ static int sis5513_tune_chipset(ide_drive_t *drive, const u8 speed)
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u32 regdw;
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u8 drive_pci, reg;
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if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4)
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return sis5513_tune_drive(drive, speed - XFER_PIO_0);
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/* See config_art_rwp_pio for drive pci config registers */
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drive_pci = 0x40;
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if (chipset_family >= ATA_133) {
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@ -139,14 +139,6 @@ static int sl82c105_tune_chipset(ide_drive_t *drive, const u8 speed)
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pci_write_config_word(dev, reg, drv_ctrl);
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}
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break;
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case XFER_PIO_5:
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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sl82c105_tune_pio(drive, speed - XFER_PIO_0);
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break;
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default:
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return -1;
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}
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@ -110,11 +110,6 @@ static int slc90e66_tune_chipset(ide_drive_t *drive, const u8 speed)
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int u_speed = 0, u_flag = 1 << drive->dn;
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u16 reg4042, reg44, reg48, reg4a;
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if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
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slc90e66_tune_pio(drive, speed - XFER_PIO_0);
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return ide_config_drive_speed(drive, speed);
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}
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pci_read_config_word(dev, maslave, ®4042);
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sitre = (reg4042 & 0x4000) ? 1 : 0;
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pci_read_config_word(dev, 0x44, ®44);
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@ -917,7 +917,7 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
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/*
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* Speedproc. This function is called by the core to set any of the standard
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* timing (PIO, MDMA or UDMA) to both the drive and the controller.
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* DMA timing (MDMA or UDMA) to both the drive and the controller.
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* You may notice we don't use this function on normal "dma check" operation,
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* our dedicated function is more precise as it uses the drive provided
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* cycle time value. We should probably fix this one to deal with that too...
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@ -964,13 +964,6 @@ static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed)
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case XFER_SW_DMA_0:
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return 1;
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#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_1:
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case XFER_PIO_0:
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pmac_ide_set_pio_mode(drive, speed & 0x07);
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return 0;
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default:
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ret = 1;
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}
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