[IA64] Perfmon for Montecito
Add Montecito PMU description table for perfmon2 Signed-off-by: Stephane Eranian <eranian@hpl.hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Stephane Eranian
Tony Luck
parent
4a8e4a270b
commit
9179cb6578
@ -628,9 +628,11 @@ static int pfm_write_ibr_dbr(int mode, pfm_context_t *ctx, void *arg, int count,
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#include "perfmon_itanium.h"
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#include "perfmon_mckinley.h"
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#include "perfmon_montecito.h"
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#include "perfmon_generic.h"
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static pmu_config_t *pmu_confs[]={
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&pmu_conf_mont,
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&pmu_conf_mck,
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&pmu_conf_ita,
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&pmu_conf_gen, /* must be last */
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269
arch/ia64/kernel/perfmon_montecito.h
Normal file
269
arch/ia64/kernel/perfmon_montecito.h
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@ -0,0 +1,269 @@
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/*
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* This file contains the Montecito PMU register description tables
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* and pmc checker used by perfmon.c.
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*
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* Copyright (c) 2005-2006 Hewlett-Packard Development Company, L.P.
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* Contributed by Stephane Eranian <eranian@hpl.hp.com>
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*/
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static int pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
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#define RDEP_MONT_ETB (RDEP(38)|RDEP(39)|RDEP(48)|RDEP(49)|RDEP(50)|RDEP(51)|RDEP(52)|RDEP(53)|RDEP(54)|\
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RDEP(55)|RDEP(56)|RDEP(57)|RDEP(58)|RDEP(59)|RDEP(60)|RDEP(61)|RDEP(62)|RDEP(63))
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#define RDEP_MONT_DEAR (RDEP(32)|RDEP(33)|RDEP(36))
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#define RDEP_MONT_IEAR (RDEP(34)|RDEP(35))
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static pfm_reg_desc_t pfm_mont_pmc_desc[PMU_MAX_PMCS]={
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/* pmc0 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc1 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc2 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc3 */ { PFM_REG_CONTROL , 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc4 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(4),0, 0, 0}, {0,0, 0, 0}},
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/* pmc5 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(5),0, 0, 0}, {0,0, 0, 0}},
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/* pmc6 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(6),0, 0, 0}, {0,0, 0, 0}},
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/* pmc7 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(7),0, 0, 0}, {0,0, 0, 0}},
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/* pmc8 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(8),0, 0, 0}, {0,0, 0, 0}},
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/* pmc9 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(9),0, 0, 0}, {0,0, 0, 0}},
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/* pmc10 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(10),0, 0, 0}, {0,0, 0, 0}},
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/* pmc11 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(11),0, 0, 0}, {0,0, 0, 0}},
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/* pmc12 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(12),0, 0, 0}, {0,0, 0, 0}},
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/* pmc13 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(13),0, 0, 0}, {0,0, 0, 0}},
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/* pmc14 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(14),0, 0, 0}, {0,0, 0, 0}},
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/* pmc15 */ { PFM_REG_COUNTING, 6, 0x2000000, 0x7c7fff7f, NULL, pfm_mont_pmc_check, {RDEP(15),0, 0, 0}, {0,0, 0, 0}},
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/* pmc16 */ { PFM_REG_NOTIMPL, },
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/* pmc17 */ { PFM_REG_NOTIMPL, },
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/* pmc18 */ { PFM_REG_NOTIMPL, },
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/* pmc19 */ { PFM_REG_NOTIMPL, },
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/* pmc20 */ { PFM_REG_NOTIMPL, },
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/* pmc21 */ { PFM_REG_NOTIMPL, },
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/* pmc22 */ { PFM_REG_NOTIMPL, },
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/* pmc23 */ { PFM_REG_NOTIMPL, },
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/* pmc24 */ { PFM_REG_NOTIMPL, },
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/* pmc25 */ { PFM_REG_NOTIMPL, },
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/* pmc26 */ { PFM_REG_NOTIMPL, },
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/* pmc27 */ { PFM_REG_NOTIMPL, },
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/* pmc28 */ { PFM_REG_NOTIMPL, },
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/* pmc29 */ { PFM_REG_NOTIMPL, },
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/* pmc30 */ { PFM_REG_NOTIMPL, },
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/* pmc31 */ { PFM_REG_NOTIMPL, },
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/* pmc32 */ { PFM_REG_CONFIG, 0, 0x30f01ffffffffff, 0x30f01ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc33 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc34 */ { PFM_REG_CONFIG, 0, 0xf01ffffffffff, 0xf01ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc35 */ { PFM_REG_CONFIG, 0, 0x0, 0x1ffffffffff, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc36 */ { PFM_REG_CONFIG, 0, 0xfffffff0, 0xf, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc37 */ { PFM_REG_MONITOR, 4, 0x0, 0x3fff, NULL, pfm_mont_pmc_check, {RDEP_MONT_IEAR, 0, 0, 0}, {0, 0, 0, 0}},
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/* pmc38 */ { PFM_REG_CONFIG, 0, 0xdb6, 0x2492, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc39 */ { PFM_REG_MONITOR, 6, 0x0, 0xffcf, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}},
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/* pmc40 */ { PFM_REG_MONITOR, 6, 0x2000000, 0xf01cf, NULL, pfm_mont_pmc_check, {RDEP_MONT_DEAR,0, 0, 0}, {0,0, 0, 0}},
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/* pmc41 */ { PFM_REG_CONFIG, 0, 0x00002078fefefefe, 0x1e00018181818, NULL, pfm_mont_pmc_check, {0,0, 0, 0}, {0,0, 0, 0}},
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/* pmc42 */ { PFM_REG_MONITOR, 6, 0x0, 0x7ff4f, NULL, pfm_mont_pmc_check, {RDEP_MONT_ETB,0, 0, 0}, {0,0, 0, 0}},
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{ PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */
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};
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static pfm_reg_desc_t pfm_mont_pmd_desc[PMU_MAX_PMDS]={
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/* pmd0 */ { PFM_REG_NOTIMPL, },
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/* pmd1 */ { PFM_REG_NOTIMPL, },
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/* pmd2 */ { PFM_REG_NOTIMPL, },
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/* pmd3 */ { PFM_REG_NOTIMPL, },
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/* pmd4 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(4),0, 0, 0}},
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/* pmd5 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(5),0, 0, 0}},
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/* pmd6 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(6),0, 0, 0}},
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/* pmd7 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(7),0, 0, 0}},
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/* pmd8 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(8),0, 0, 0}},
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/* pmd9 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(9),0, 0, 0}},
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/* pmd10 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(10),0, 0, 0}},
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/* pmd11 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(11),0, 0, 0}},
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/* pmd12 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(12),0, 0, 0}},
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/* pmd13 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(13),0, 0, 0}},
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/* pmd14 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(14),0, 0, 0}},
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/* pmd15 */ { PFM_REG_COUNTING, 0, 0x0, -1, NULL, NULL, {0,0, 0, 0}, {RDEP(15),0, 0, 0}},
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/* pmd16 */ { PFM_REG_NOTIMPL, },
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/* pmd17 */ { PFM_REG_NOTIMPL, },
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/* pmd18 */ { PFM_REG_NOTIMPL, },
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/* pmd19 */ { PFM_REG_NOTIMPL, },
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/* pmd20 */ { PFM_REG_NOTIMPL, },
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/* pmd21 */ { PFM_REG_NOTIMPL, },
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/* pmd22 */ { PFM_REG_NOTIMPL, },
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/* pmd23 */ { PFM_REG_NOTIMPL, },
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/* pmd24 */ { PFM_REG_NOTIMPL, },
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/* pmd25 */ { PFM_REG_NOTIMPL, },
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/* pmd26 */ { PFM_REG_NOTIMPL, },
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/* pmd27 */ { PFM_REG_NOTIMPL, },
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/* pmd28 */ { PFM_REG_NOTIMPL, },
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/* pmd29 */ { PFM_REG_NOTIMPL, },
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/* pmd30 */ { PFM_REG_NOTIMPL, },
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/* pmd31 */ { PFM_REG_NOTIMPL, },
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/* pmd32 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(33)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}},
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/* pmd33 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(36),0, 0, 0}, {RDEP(40),0, 0, 0}},
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/* pmd34 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(35),0, 0, 0}, {RDEP(37),0, 0, 0}},
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/* pmd35 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(34),0, 0, 0}, {RDEP(37),0, 0, 0}},
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/* pmd36 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP(32)|RDEP(33),0, 0, 0}, {RDEP(40),0, 0, 0}},
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/* pmd37 */ { PFM_REG_NOTIMPL, },
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/* pmd38 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd39 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd40 */ { PFM_REG_NOTIMPL, },
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/* pmd41 */ { PFM_REG_NOTIMPL, },
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/* pmd42 */ { PFM_REG_NOTIMPL, },
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/* pmd43 */ { PFM_REG_NOTIMPL, },
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/* pmd44 */ { PFM_REG_NOTIMPL, },
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/* pmd45 */ { PFM_REG_NOTIMPL, },
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/* pmd46 */ { PFM_REG_NOTIMPL, },
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/* pmd47 */ { PFM_REG_NOTIMPL, },
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/* pmd48 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd49 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd50 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd51 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd52 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd53 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd54 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd55 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd56 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd57 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd58 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd59 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd60 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd61 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd62 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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/* pmd63 */ { PFM_REG_BUFFER, 0, 0x0, -1, NULL, NULL, {RDEP_MONT_ETB,0, 0, 0}, {RDEP(39),0, 0, 0}},
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{ PFM_REG_END , 0, 0x0, -1, NULL, NULL, {0,}, {0,}}, /* end marker */
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};
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/*
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* PMC reserved fields must have their power-up values preserved
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*/
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static int
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pfm_mont_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs)
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{
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unsigned long tmp1, tmp2, ival = *val;
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/* remove reserved areas from user value */
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tmp1 = ival & PMC_RSVD_MASK(cnum);
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/* get reserved fields values */
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tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum);
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*val = tmp1 | tmp2;
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DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n",
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cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val));
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return 0;
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}
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/*
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* task can be NULL if the context is unloaded
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*/
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static int
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pfm_mont_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
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{
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int ret = 0;
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unsigned long val32 = 0, val38 = 0, val41 = 0;
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unsigned long tmpval;
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int check_case1 = 0;
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int is_loaded;
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/* first preserve the reserved fields */
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pfm_mont_reserved(cnum, val, regs);
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tmpval = *val;
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/* sanity check */
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if (ctx == NULL) return -EINVAL;
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is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED;
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/*
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* we must clear the debug registers if pmc41 has a value which enable
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* memory pipeline event constraints. In this case we need to clear the
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* the debug registers if they have not yet been accessed. This is required
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* to avoid picking stale state.
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* PMC41 is "active" if:
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* one of the pmc41.cfg_dtagXX field is different from 0x3
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* AND
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* at the corresponding pmc41.en_dbrpXX is set.
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* AND
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* ctx_fl_using_dbreg == 0 (i.e., dbr not yet used)
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*/
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DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, tmpval, ctx->ctx_fl_using_dbreg, is_loaded));
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if (cnum == 41 && is_loaded
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&& (tmpval & 0x1e00000000000) && (tmpval & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) {
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DPRINT(("pmc[%d]=0x%lx has active pmc41 settings, clearing dbr\n", cnum, tmpval));
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/* don't mix debug with perfmon */
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if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
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/*
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* a count of 0 will mark the debug registers if:
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* AND
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*/
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ret = pfm_write_ibr_dbr(PFM_DATA_RR, ctx, NULL, 0, regs);
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if (ret) return ret;
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}
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/*
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* we must clear the (instruction) debug registers if:
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* pmc38.ig_ibrpX is 0 (enabled)
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* AND
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* ctx_fl_using_dbreg == 0 (i.e., dbr not yet used)
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*/
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if (cnum == 38 && is_loaded && ((tmpval & 0x492UL) != 0x492UL) && ctx->ctx_fl_using_dbreg == 0) {
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DPRINT(("pmc38=0x%lx has active pmc38 settings, clearing ibr\n", tmpval));
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/* don't mix debug with perfmon */
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if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
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/*
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* a count of 0 will mark the debug registers as in use and also
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* ensure that they are properly cleared.
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*/
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ret = pfm_write_ibr_dbr(PFM_CODE_RR, ctx, NULL, 0, regs);
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if (ret) return ret;
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}
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switch(cnum) {
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case 32: val32 = *val;
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val38 = ctx->ctx_pmcs[38];
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val41 = ctx->ctx_pmcs[41];
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check_case1 = 1;
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break;
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case 38: val38 = *val;
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val32 = ctx->ctx_pmcs[32];
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val41 = ctx->ctx_pmcs[41];
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check_case1 = 1;
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break;
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case 41: val41 = *val;
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val32 = ctx->ctx_pmcs[32];
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val38 = ctx->ctx_pmcs[38];
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check_case1 = 1;
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break;
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}
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/* check illegal configuration which can produce inconsistencies in tagging
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* i-side events in L1D and L2 caches
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*/
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if (check_case1) {
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ret = (((val41 >> 45) & 0xf) == 0 && ((val32>>57) & 0x1) == 0)
|
||||
&& ((((val38>>1) & 0x3) == 0x2 || ((val38>>1) & 0x3) == 0)
|
||||
|| (((val38>>4) & 0x3) == 0x2 || ((val38>>4) & 0x3) == 0));
|
||||
if (ret) {
|
||||
DPRINT(("invalid config pmc38=0x%lx pmc41=0x%lx pmc32=0x%lx\n", val38, val41, val32));
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
*val = tmpval;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* impl_pmcs, impl_pmds are computed at runtime to minimize errors!
|
||||
*/
|
||||
static pmu_config_t pmu_conf_mont={
|
||||
.pmu_name = "Montecito",
|
||||
.pmu_family = 0x20,
|
||||
.flags = PFM_PMU_IRQ_RESEND,
|
||||
.ovfl_val = (1UL << 47) - 1,
|
||||
.pmd_desc = pfm_mont_pmd_desc,
|
||||
.pmc_desc = pfm_mont_pmc_desc,
|
||||
.num_ibrs = 8,
|
||||
.num_dbrs = 8,
|
||||
.use_rr_dbregs = 1 /* debug register are use for range retrictions */
|
||||
};
|
||||
@ -25,8 +25,8 @@
|
||||
* Limits for PMC and PMD are set to less than maximum architected values
|
||||
* but should be sufficient for a while
|
||||
*/
|
||||
#define IA64_NUM_PMC_REGS 32
|
||||
#define IA64_NUM_PMD_REGS 32
|
||||
#define IA64_NUM_PMC_REGS 64
|
||||
#define IA64_NUM_PMD_REGS 64
|
||||
|
||||
#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
|
||||
#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user