sh: Provide common CPU headers, prune the SH-2 and SH-2A directories.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
1795cf48b3
commit
93dc544cf4
@ -91,7 +91,6 @@ LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64+4'
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LDFLAGS += -EB
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endif
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head-y := arch/sh/kernel/init_task.o
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head-$(CONFIG_SUPERH32) += arch/sh/kernel/head_32.o
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head-$(CONFIG_SUPERH64) += arch/sh/kernel/head_64.o
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@ -134,11 +133,22 @@ endif
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# Companion chips
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core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/
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cpuincdir-$(CONFIG_CPU_SH2) := cpu-sh2
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cpuincdir-$(CONFIG_CPU_SH2A) := cpu-sh2a
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cpuincdir-$(CONFIG_CPU_SH3) := cpu-sh3
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cpuincdir-$(CONFIG_CPU_SH4) := cpu-sh4
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cpuincdir-$(CONFIG_CPU_SH5) := cpu-sh5
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#
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# CPU header paths
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#
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# These are ordered by optimization level. A CPU family that is a subset
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# of another (ie, SH-2A / SH-2), is picked up first, with increasing
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# levels of genericness if nothing more suitable is situated in the
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# hierarchy.
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#
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# As an example, in order of preference, SH-2A > SH-2 > common definitions.
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#
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cpuincdir-$(CONFIG_CPU_SH2A) += cpu-sh2a
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cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2
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cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3
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cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4
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cpuincdir-$(CONFIG_CPU_SH5) += cpu-sh5
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cpuincdir-y += cpu-common # Must be last
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libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y)
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libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y)
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@ -149,8 +159,8 @@ drivers-$(CONFIG_OPROFILE) += arch/sh/oprofile/
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boot := arch/sh/boot
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cflags-y += -Iarch/sh/include/$(cpuincdir-y)
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cflags-y += $(foreach d, $(machdir-y), -Iarch/sh/include/$(d))
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cflags-y += $(foreach d, $(cpuincdir-y), -Iarch/sh/include/$(d)) \
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$(foreach d, $(machdir-y), -Iarch/sh/include/$(d))
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KBUILD_CFLAGS += -pipe $(cflags-y)
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KBUILD_CPPFLAGS += $(cflags-y)
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@ -40,5 +40,5 @@
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#define flush_cache_sigtramp(vaddr) do { } while (0)
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#define p3_cache_init() do { } while (0)
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#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */
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#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */
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@ -1,10 +0,0 @@
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#ifndef __ASM_SH_CPU_SH2A_ADDRSPACE_H
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#define __ASM_SH_CPU_SH2A_ADDRSPACE_H
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#define P0SEG 0x00000000
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#define P1SEG 0x00000000
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#define P2SEG 0x20000000
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#define P3SEG 0x00000000
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#define P4SEG 0x80000000
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#endif /* __ASM_SH_CPU_SH2A_ADDRSPACE_H */
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@ -1,44 +0,0 @@
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/*
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* include/asm-sh/cpu-sh2/cacheflush.h
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*
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH2_CACHEFLUSH_H
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#define __ASM_CPU_SH2_CACHEFLUSH_H
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/*
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* Cache flushing:
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*
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* - flush_cache_all() flushes entire cache
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* - flush_cache_mm(mm) flushes the specified mm context's cache lines
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* - flush_cache_dup mm(mm) handles cache flushing when forking
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* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
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* - flush_cache_range(vma, start, end) flushes a range of pages
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*
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* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
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* - flush_icache_range(start, end) flushes(invalidates) a range for icache
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* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
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*
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* Caches are indexed (effectively) by physical address on SH-2, so
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* we don't need them.
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_range(start, end) do { } while (0)
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#define flush_icache_page(vma,pg) do { } while (0)
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define flush_cache_sigtramp(vaddr) do { } while (0)
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#define p3_cache_init() do { } while (0)
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#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */
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@ -1,23 +1 @@
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/*
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* Definitions for the SH-2 DMAC.
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*
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH2_DMA_H
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#define __ASM_CPU_SH2_DMA_H
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#define SH_MAX_DMA_CHANNELS 2
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#define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 })
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#define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 })
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#define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 })
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#define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
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#define DMAOR 0xffffffb0
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#endif /* __ASM_CPU_SH2_DMA_H */
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#include <cpu-sh2/cpu/dma.h>
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@ -1,16 +0,0 @@
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/*
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* include/asm-sh/cpu-sh2/mmu_context.h
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*
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
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#define __ASM_CPU_SH2_MMU_CONTEXT_H
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/* No MMU */
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#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */
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@ -1,6 +0,0 @@
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#ifndef __ASM_CPU_SH2_TIMER_H
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#define __ASM_CPU_SH2_TIMER_H
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/* Nothing needed yet */
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#endif /* __ASM_CPU_SH2_TIMER_H */
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@ -1,32 +1 @@
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/*
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* include/asm-sh/cpu-sh2/ubc.h
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*
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH2_UBC_H
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#define __ASM_CPU_SH2_UBC_H
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#define UBC_BARA 0xffffff40
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#define UBC_BAMRA 0xffffff44
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#define UBC_BBRA 0xffffff48
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#define UBC_BARB 0xffffff60
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#define UBC_BAMRB 0xffffff64
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#define UBC_BBRB 0xffffff68
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#define UBC_BDRB 0xffffff70
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#define UBC_BDMRB 0xffffff74
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#define UBC_BRCR 0xffffff78
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/*
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* We don't have any ASID changes to make in the UBC on the SH-2.
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*
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* Make these purposely invalid to track misuse.
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*/
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#define UBC_BASRA 0x00000000
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#define UBC_BASRB 0x00000000
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#endif /* __ASM_CPU_SH2_UBC_H */
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#include <cpu-sh2/cpu/ubc.h>
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@ -1,69 +1 @@
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/*
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* include/asm-sh/cpu-sh2/watchdog.h
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*
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* Copyright (C) 2002, 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH2_WATCHDOG_H
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#define __ASM_CPU_SH2_WATCHDOG_H
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/*
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* More SH-2 brilliance .. its not good enough that we can't read
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* and write the same sizes to WTCNT, now we have to read and write
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* with different sizes at different addresses for WTCNT _and_ RSTCSR.
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*
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* At least on the bright side no one has managed to screw over WTCSR
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* in this fashion .. yet.
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*/
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/* Register definitions */
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#define WTCNT 0xfffffe80
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#define WTCSR 0xfffffe80
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#define RSTCSR 0xfffffe82
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#define WTCNT_R (WTCNT + 1)
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#define RSTCSR_R (RSTCSR + 1)
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/* Bit definitions */
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#define WTCSR_IOVF 0x80
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#define WTCSR_WT 0x40
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#define WTCSR_TME 0x20
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#define WTCSR_RSTS 0x00
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#define RSTCSR_RSTS 0x20
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/**
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* sh_wdt_read_rstcsr - Read from Reset Control/Status Register
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*
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* Reads back the RSTCSR value.
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*/
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static inline __u8 sh_wdt_read_rstcsr(void)
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{
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/*
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* Same read/write brain-damage as for WTCNT here..
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*/
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return ctrl_inb(RSTCSR_R);
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}
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/**
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* sh_wdt_write_csr - Write to Reset Control/Status Register
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*
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* @val: Value to write
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*
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* Writes the given value @val to the lower byte of the control/status
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* register. The upper byte is set manually on each write.
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*/
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static inline void sh_wdt_write_rstcsr(__u8 val)
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{
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/*
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* Note: Due to the brain-damaged nature of this register,
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* we can't presently touch the WOVF bit, since the upper byte
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* has to be swapped for this. So just leave it alone..
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*/
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ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
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}
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#endif /* __ASM_CPU_SH2_WATCHDOG_H */
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#include <cpu-sh2/cpu/watchdog.h>
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