Blackfin: SMP: make all barriers handle cache issues
When suspending/resuming, the common task freezing code will run in parallel and freeze processes on each core. This is because the code uses the non-smp version of memory barriers (as well it should). The Blackfin smp barrier logic at the moment contains the cache sync logic, but the non-smp barriers do not. This is incorrect as Rafel summarized: > ... > The existing memory barriers are SMP barriers too, but they are more > than _just_ SMP barriers. At least that's how it is _supposed_ to be > (eg. rmb() is supposed to be stronger than smp_rmb()). > ... > However, looking at the blackfin's definitions of SMP barriers I see > that it uses extra stuff that should _also_ be used in the definitions > of the mandatory barriers. > ... URL: http://lkml.org/lkml/2011/4/13/11 LKML-Reference: <BANLkTi=F-C-vwX4PGGfbkdTBw3OWL-twfg@mail.gmail.com> Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -19,11 +19,11 @@
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* Force strict CPU ordering.
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*/
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#define nop() __asm__ __volatile__ ("nop;\n\t" : : )
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#define mb() __asm__ __volatile__ ("" : : : "memory")
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#define rmb() __asm__ __volatile__ ("" : : : "memory")
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#define wmb() __asm__ __volatile__ ("" : : : "memory")
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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#define read_barrier_depends() do { } while(0)
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define smp_read_barrier_depends() read_barrier_depends()
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#ifdef CONFIG_SMP
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asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
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@ -37,16 +37,16 @@ asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
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unsigned long new, unsigned long old);
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#ifdef __ARCH_SYNC_CORE_DCACHE
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# define smp_mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
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# define smp_rmb() do { barrier(); smp_check_barrier(); } while (0)
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# define smp_wmb() do { barrier(); smp_mark_barrier(); } while (0)
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#define smp_read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
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/* Force Core data cache coherence */
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# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
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# define rmb() do { barrier(); smp_check_barrier(); } while (0)
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# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
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# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
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#else
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# define smp_mb() barrier()
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# define smp_rmb() barrier()
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# define smp_wmb() barrier()
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#define smp_read_barrier_depends() barrier()
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# define mb() barrier()
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# define rmb() barrier()
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# define wmb() barrier()
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# define read_barrier_depends() do { } while (0)
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#endif
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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@ -99,10 +99,10 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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#else /* !CONFIG_SMP */
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define read_barrier_depends() do { } while (0)
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struct __xchg_dummy {
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unsigned long a[100];
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