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MIPS: Malta: Let PIIX4 respond to PCI special cycles

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This patch enables the PIIX4 to respond to special cycles on the PCI
bus. One such special cycle must be used in order to enter a suspend
state, and if response to it is not enabled then the suspend state will
never be entered.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6904/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton 2014-05-07 12:20:58 +01:00 committed by Ralf Baechle
parent b6911bba59
commit 9e53481eea
1 changed files with 6 additions and 0 deletions
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6
arch/mips/pci/fixup-malta.c
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@ -68,6 +68,7 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
{ {
unsigned char reg_val; unsigned char reg_val;
u32 reg_val32; u32 reg_val32;
u16 reg_val16;
/* PIIX PIRQC[A:D] irq mappings */ /* PIIX PIRQC[A:D] irq mappings */
static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = { static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
0, 0, 0, 3, 0, 0, 0, 3,
@ -107,6 +108,11 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
/* Enable response to special cycles */
pci_read_config_word(pdev, PCI_COMMAND, &reg_val16);
pci_write_config_word(pdev, PCI_COMMAND,
reg_val16 | PCI_COMMAND_SPECIAL);
} }
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,