Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging
* 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging: hwmon: (lm85) extend to support EMC6D103 chips MAINTAINERS: Remove stale hwmon quilt tree hwmon: (k10temp) add support for AMD Family 12h/14h CPUs hwmon: (jc42) do not allow writing to locked registers hwmon: (jc42) more helpful documentation hwmon: (jc42) fix type mismatch
This commit is contained in:
Linus Torvalds
commit
a0c85e96d3
@ -51,7 +51,8 @@ Supported chips:
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* JEDEC JC 42.4 compliant temperature sensor chips
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Prefix: 'jc42'
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Addresses scanned: I2C 0x18 - 0x1f
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Datasheet: -
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Datasheet:
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http://www.jedec.org/sites/default/files/docs/4_01_04R19.pdf
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Author:
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Guenter Roeck <guenter.roeck@ericsson.com>
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@ -60,7 +61,11 @@ Author:
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Description
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-----------
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This driver implements support for JEDEC JC 42.4 compliant temperature sensors.
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This driver implements support for JEDEC JC 42.4 compliant temperature sensors,
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which are used on many DDR3 memory modules for mobile devices and servers. Some
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systems use the sensor to prevent memory overheating by automatically throttling
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the memory controller.
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The driver auto-detects the chips listed above, but can be manually instantiated
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to support other JC 42.4 compliant chips.
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@ -81,15 +86,19 @@ limits. The chip supports only a single register to configure the hysteresis,
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which applies to all limits. This register can be written by writing into
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temp1_crit_hyst. Other hysteresis attributes are read-only.
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If the BIOS has configured the sensor for automatic temperature management, it
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is likely that it has locked the registers, i.e., that the temperature limits
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cannot be changed.
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Sysfs entries
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-------------
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temp1_input Temperature (RO)
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temp1_min Minimum temperature (RW)
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temp1_max Maximum temperature (RW)
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temp1_crit Critical high temperature (RW)
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temp1_min Minimum temperature (RO or RW)
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temp1_max Maximum temperature (RO or RW)
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temp1_crit Critical high temperature (RO or RW)
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temp1_crit_hyst Critical hysteresis temperature (RW)
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temp1_crit_hyst Critical hysteresis temperature (RO or RW)
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temp1_max_hyst Maximum hysteresis temperature (RO)
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temp1_min_alarm Temperature low alarm
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@ -9,6 +9,8 @@ Supported chips:
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Socket S1G3: Athlon II, Sempron, Turion II
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* AMD Family 11h processors:
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Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
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* AMD Family 12h processors: "Llano"
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* AMD Family 14h processors: "Brazos" (C/E/G-Series)
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Prefix: 'k10temp'
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Addresses scanned: PCI space
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@ -17,10 +19,14 @@ Supported chips:
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http://support.amd.com/us/Processor_TechDocs/31116.pdf
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BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors:
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http://support.amd.com/us/Processor_TechDocs/41256.pdf
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BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
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http://support.amd.com/us/Processor_TechDocs/43170.pdf
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Revision Guide for AMD Family 10h Processors:
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http://support.amd.com/us/Processor_TechDocs/41322.pdf
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Revision Guide for AMD Family 11h Processors:
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http://support.amd.com/us/Processor_TechDocs/41788.pdf
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Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
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http://support.amd.com/us/Processor_TechDocs/47534.pdf
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AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:
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http://support.amd.com/us/Processor_TechDocs/43373.pdf
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AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
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@ -34,7 +40,7 @@ Description
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-----------
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This driver permits reading of the internal temperature sensor of AMD
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Family 10h and 11h processors.
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Family 10h/11h/12h/14h processors.
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All these processors have a sensor, but on those for Socket F or AM2+,
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the sensor may return inconsistent values (erratum 319). The driver
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@ -2873,7 +2873,6 @@ M: Guenter Roeck <guenter.roeck@ericsson.com>
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L: lm-sensors@lm-sensors.org
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W: http://www.lm-sensors.org/
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T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
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T: quilt kernel.org/pub/linux/kernel/people/groeck/linux-staging/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
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S: Maintained
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F: Documentation/hwmon/
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@ -238,13 +238,13 @@ config SENSORS_K8TEMP
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will be called k8temp.
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config SENSORS_K10TEMP
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tristate "AMD Phenom/Sempron/Turion/Opteron temperature sensor"
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tristate "AMD Family 10h/11h/12h/14h temperature sensor"
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depends on X86 && PCI
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help
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If you say yes here you get support for the temperature
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sensor(s) inside your CPU. Supported are later revisions of
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the AMD Family 10h and all revisions of the AMD Family 11h
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microarchitectures.
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the AMD Family 10h and all revisions of the AMD Family 11h,
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12h (Llano), and 14h (Brazos) microarchitectures.
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This driver can also be built as a module. If so, the module
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will be called k10temp.
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@ -455,13 +455,14 @@ config SENSORS_JZ4740
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called jz4740-hwmon.
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config SENSORS_JC42
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tristate "JEDEC JC42.4 compliant temperature sensors"
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tristate "JEDEC JC42.4 compliant memory module temperature sensors"
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depends on I2C
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help
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If you say yes here you get support for Jedec JC42.4 compliant
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temperature sensors. Support will include, but not be limited to,
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ADT7408, CAT34TS02,, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243,
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MCP9843, SE97, SE98, STTS424, TSE2002B3, and TS3000B3.
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If you say yes here, you get support for JEDEC JC42.4 compliant
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temperature sensors, which are used on many DDR3 memory modules for
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mobile devices and servers. Support will include, but not be limited
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to, ADT7408, CAT34TS02, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243,
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MCP9843, SE97, SE98, STTS424(E), TSE2002B3, and TS3000B3.
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This driver can also be built as a module. If so, the module
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will be called jc42.
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@ -574,7 +575,7 @@ config SENSORS_LM85
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help
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If you say yes here you get support for National Semiconductor LM85
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sensor chips and clones: ADM1027, ADT7463, ADT7468, EMC6D100,
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EMC6D101 and EMC6D102.
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EMC6D101, EMC6D102, and EMC6D103.
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This driver can also be built as a module. If so, the module
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will be called lm85.
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@ -53,6 +53,8 @@ static const unsigned short normal_i2c[] = {
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/* Configuration register defines */
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#define JC42_CFG_CRIT_ONLY (1 << 2)
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#define JC42_CFG_TCRIT_LOCK (1 << 6)
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#define JC42_CFG_EVENT_LOCK (1 << 7)
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#define JC42_CFG_SHUTDOWN (1 << 8)
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#define JC42_CFG_HYST_SHIFT 9
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#define JC42_CFG_HYST_MASK 0x03
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@ -332,7 +334,7 @@ static ssize_t set_temp_crit_hyst(struct device *dev,
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{
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struct i2c_client *client = to_i2c_client(dev);
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struct jc42_data *data = i2c_get_clientdata(client);
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long val;
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unsigned long val;
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int diff, hyst;
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int err;
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int ret = count;
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@ -380,14 +382,14 @@ static ssize_t show_alarm(struct device *dev,
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static DEVICE_ATTR(temp1_input, S_IRUGO,
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show_temp_input, NULL);
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static DEVICE_ATTR(temp1_crit, S_IWUSR | S_IRUGO,
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static DEVICE_ATTR(temp1_crit, S_IRUGO,
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show_temp_crit, set_temp_crit);
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static DEVICE_ATTR(temp1_min, S_IWUSR | S_IRUGO,
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static DEVICE_ATTR(temp1_min, S_IRUGO,
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show_temp_min, set_temp_min);
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static DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO,
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static DEVICE_ATTR(temp1_max, S_IRUGO,
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show_temp_max, set_temp_max);
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static DEVICE_ATTR(temp1_crit_hyst, S_IWUSR | S_IRUGO,
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static DEVICE_ATTR(temp1_crit_hyst, S_IRUGO,
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show_temp_crit_hyst, set_temp_crit_hyst);
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static DEVICE_ATTR(temp1_max_hyst, S_IRUGO,
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show_temp_max_hyst, NULL);
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@ -412,8 +414,31 @@ static struct attribute *jc42_attributes[] = {
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NULL
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};
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static mode_t jc42_attribute_mode(struct kobject *kobj,
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struct attribute *attr, int index)
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{
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struct device *dev = container_of(kobj, struct device, kobj);
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struct i2c_client *client = to_i2c_client(dev);
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struct jc42_data *data = i2c_get_clientdata(client);
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unsigned int config = data->config;
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bool readonly;
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if (attr == &dev_attr_temp1_crit.attr)
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readonly = config & JC42_CFG_TCRIT_LOCK;
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else if (attr == &dev_attr_temp1_min.attr ||
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attr == &dev_attr_temp1_max.attr)
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readonly = config & JC42_CFG_EVENT_LOCK;
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else if (attr == &dev_attr_temp1_crit_hyst.attr)
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readonly = config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK);
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else
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readonly = true;
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return S_IRUGO | (readonly ? 0 : S_IWUSR);
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}
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static const struct attribute_group jc42_group = {
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.attrs = jc42_attributes,
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.is_visible = jc42_attribute_mode,
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};
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/* Return 0 if detection is successful, -ENODEV otherwise */
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@ -1,5 +1,5 @@
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/*
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* k10temp.c - AMD Family 10h/11h processor hardware monitoring
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* k10temp.c - AMD Family 10h/11h/12h/14h processor hardware monitoring
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*
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* Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
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*
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@ -25,7 +25,7 @@
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#include <linux/pci.h>
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#include <asm/processor.h>
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MODULE_DESCRIPTION("AMD Family 10h/11h CPU core temperature monitor");
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MODULE_DESCRIPTION("AMD Family 10h/11h/12h/14h CPU core temperature monitor");
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MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
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MODULE_LICENSE("GPL");
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@ -208,6 +208,7 @@ static void __devexit k10temp_remove(struct pci_dev *pdev)
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static const struct pci_device_id k10temp_id_table[] = {
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
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{}
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};
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MODULE_DEVICE_TABLE(pci, k10temp_id_table);
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@ -41,7 +41,7 @@ static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END };
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enum chips {
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any_chip, lm85b, lm85c,
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adm1027, adt7463, adt7468,
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emc6d100, emc6d102
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emc6d100, emc6d102, emc6d103
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};
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/* The LM85 registers */
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@ -90,6 +90,9 @@ enum chips {
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#define LM85_VERSTEP_EMC6D100_A0 0x60
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#define LM85_VERSTEP_EMC6D100_A1 0x61
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#define LM85_VERSTEP_EMC6D102 0x65
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#define LM85_VERSTEP_EMC6D103_A0 0x68
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#define LM85_VERSTEP_EMC6D103_A1 0x69
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#define LM85_VERSTEP_EMC6D103S 0x6A /* Also known as EMC6D103:A2 */
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#define LM85_REG_CONFIG 0x40
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@ -348,6 +351,7 @@ static const struct i2c_device_id lm85_id[] = {
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{ "emc6d100", emc6d100 },
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{ "emc6d101", emc6d100 },
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{ "emc6d102", emc6d102 },
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{ "emc6d103", emc6d103 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, lm85_id);
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@ -1250,6 +1254,20 @@ static int lm85_detect(struct i2c_client *client, struct i2c_board_info *info)
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case LM85_VERSTEP_EMC6D102:
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type_name = "emc6d102";
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break;
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case LM85_VERSTEP_EMC6D103_A0:
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case LM85_VERSTEP_EMC6D103_A1:
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type_name = "emc6d103";
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break;
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/*
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* Registers apparently missing in EMC6D103S/EMC6D103:A2
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* compared to EMC6D103:A0, EMC6D103:A1, and EMC6D102
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* (according to the data sheets), but used unconditionally
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* in the driver: 62[5:7], 6D[0:7], and 6E[0:7].
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* So skip EMC6D103S for now.
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case LM85_VERSTEP_EMC6D103S:
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type_name = "emc6d103s";
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break;
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*/
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}
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} else {
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dev_dbg(&adapter->dev,
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@ -1283,6 +1301,7 @@ static int lm85_probe(struct i2c_client *client,
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case adt7468:
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case emc6d100:
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case emc6d102:
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case emc6d103:
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data->freq_map = adm1027_freq_map;
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break;
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default:
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@ -1468,7 +1487,7 @@ static struct lm85_data *lm85_update_device(struct device *dev)
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/* More alarm bits */
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data->alarms |= lm85_read_value(client,
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EMC6D100_REG_ALARM3) << 16;
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} else if (data->type == emc6d102) {
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} else if (data->type == emc6d102 || data->type == emc6d103) {
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/* Have to read LSB bits after the MSB ones because
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the reading of the MSB bits has frozen the
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LSBs (backward from the ADM1027).
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