drm/radeon: properly set vm fragment size for TN/RL
Should be the same as cayman. We don't use VM by default on NI parts so this isn't critical. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -743,9 +743,11 @@ static void radeon_vm_frag_ptes(struct radeon_device *rdev,
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*/
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/* NI is optimized for 256KB fragments, SI and newer for 64KB */
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uint64_t frag_flags = rdev->family == CHIP_CAYMAN ?
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uint64_t frag_flags = ((rdev->family == CHIP_CAYMAN) ||
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(rdev->family == CHIP_ARUBA)) ?
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R600_PTE_FRAG_256KB : R600_PTE_FRAG_64KB;
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uint64_t frag_align = rdev->family == CHIP_CAYMAN ? 0x200 : 0x80;
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uint64_t frag_align = ((rdev->family == CHIP_CAYMAN) ||
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(rdev->family == CHIP_ARUBA)) ? 0x200 : 0x80;
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uint64_t frag_start = ALIGN(pe_start, frag_align);
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uint64_t frag_end = pe_end & ~(frag_align - 1);
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