Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull clocksource updates from Ingo Molnar: "Misc clocksource/clockevent driver updates that came in a bit late but are ready for v5.2" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: misc: atmel_tclib: Do not probe already used TCBs clocksource/drivers/timer-atmel-tcb: Convert tc_clksrc_suspend|resume() to static clocksource/drivers/tcb_clksrc: Rename the file for consistency clocksource/drivers/timer-atmel-pit: Rework Kconfig option clocksource/drivers/tcb_clksrc: Move Kconfig option ARM: at91: Implement clocksource selection clocksource/drivers/tcb_clksrc: Use tcb as sched_clock clocksource/drivers/tcb_clksrc: Stop depending on atmel_tclib ARM: at91: move SoC specific definitions to SoC folder clocksource/drivers/timer-milbeaut: Cleanup common register accesses clocksource/drivers/timer-milbeaut: Add shutdown function clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer clocksource/drivers/tegra: Rework for compensation of suspend time clocksource/drivers/sp804: Add COMPILE_TEST to CONFIG_ARM_TIMER_SP804 clocksource/drivers/sun4i: Add a compatible for suniv dt-bindings: timer: Add Allwinner suniv timer
This commit is contained in:
Linus Torvalds
commit
a13f950ef1
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@ -2,7 +2,9 @@ Allwinner A1X SoCs Timer Controller
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Required properties:
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- compatible : should be "allwinner,sun4i-a10-timer"
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- compatible : should be one of the following:
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"allwinner,sun4i-a10-timer"
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"allwinner,suniv-f1c100s-timer"
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- reg : Specifies base physical address and size of the registers.
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- interrupts : The interrupt of the first timer
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- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
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@ -104,6 +104,29 @@ config SOC_AT91SAM9
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AT91SAM9X35
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AT91SAM9XE
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comment "Clocksource driver selection"
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config ATMEL_CLOCKSOURCE_PIT
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bool "Periodic Interval Timer (PIT) support"
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depends on SOC_AT91SAM9 || SOC_SAMA5
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default SOC_AT91SAM9 || SOC_SAMA5
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select ATMEL_PIT
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help
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Select this to get a clocksource based on the Atmel Periodic Interval
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Timer. It has a relatively low resolution and the TC Block clocksource
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should be preferred.
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config ATMEL_CLOCKSOURCE_TCB
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bool "Timer Counter Blocks (TCB) support"
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default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAMA5
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select ATMEL_TCB_CLKSRC
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help
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Select this to get a high precision clocksource based on a
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TC block with a 5+ MHz base clock rate.
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On platforms with 16-bit counters, two timer channels are combined
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to make a single 32-bit timer.
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It can also be used as a clock event device supporting oneshot mode.
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config HAVE_AT91_UTMI
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bool
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@ -387,7 +387,7 @@ config ARM_GLOBAL_TIMER
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This options enables support for the ARM global timer unit
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config ARM_TIMER_SP804
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bool "Support for Dual Timer SP804 module"
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bool "Support for Dual Timer SP804 module" if COMPILE_TEST
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depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select TIMER_OF if OF
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@ -407,8 +407,11 @@ config ARMV7M_SYSTICK
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This options enables support for the ARMv7M system timer unit
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config ATMEL_PIT
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bool "Atmel PIT support" if COMPILE_TEST
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depends on HAS_IOMEM
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select TIMER_OF if OF
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def_bool SOC_AT91SAM9 || SOC_SAMA5
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help
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Support for the Periodic Interval Timer found on Atmel SoCs.
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config ATMEL_ST
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bool "Atmel ST timer support" if COMPILE_TEST
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@ -418,6 +421,13 @@ config ATMEL_ST
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help
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Support for the Atmel ST timer.
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config ATMEL_TCB_CLKSRC
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bool "Atmel TC Block timer driver" if COMPILE_TEST
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depends on HAS_IOMEM
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select TIMER_OF if OF
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help
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Support for Timer Counter Blocks on Atmel SoCs.
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config CLKSRC_EXYNOS_MCT
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bool "Exynos multi core timer driver" if COMPILE_TEST
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depends on ARM || ARM64
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@ -3,7 +3,7 @@ obj-$(CONFIG_TIMER_OF) += timer-of.o
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obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
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obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
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obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
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obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
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obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o
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obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
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obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
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obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o
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@ -9,9 +9,11 @@
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/syscore_ops.h>
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#include <linux/atmel_tc.h>
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#include <soc/at91/atmel_tcb.h>
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/*
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@ -28,13 +30,6 @@
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* source, used in either periodic or oneshot mode. This runs
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* at 32 KiHZ, and can handle delays of up to two seconds.
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*
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* A boot clocksource and clockevent source are also currently needed,
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* unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
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* this code can be used when init_timers() is called, well before most
|
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* devices are set up. (Some low end AT91 parts, which can run uClinux,
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* have only the timers in one TC block... they currently don't support
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||||
* the tclib code, because of that initialization issue.)
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*
|
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* REVISIT behavior during system suspend states... we should disable
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* all clocks and save the power. Easily done for clockevent devices,
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* but clocksources won't necessarily get the needed notifications.
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@ -112,7 +107,6 @@ static void tc_clksrc_resume(struct clocksource *cs)
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}
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static struct clocksource clksrc = {
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.name = "tcb_clksrc",
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.rating = 200,
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.read = tc_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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@ -121,6 +115,16 @@ static struct clocksource clksrc = {
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.resume = tc_clksrc_resume,
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};
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static u64 notrace tc_sched_clock_read(void)
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{
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return tc_get_cycles(&clksrc);
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}
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static u64 notrace tc_sched_clock_read32(void)
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{
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return tc_get_cycles32(&clksrc);
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}
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#ifdef CONFIG_GENERIC_CLOCKEVENTS
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struct tc_clkevt_device {
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@ -214,7 +218,6 @@ static int tc_next_event(unsigned long delta, struct clock_event_device *d)
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static struct tc_clkevt_device clkevt = {
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.clkevt = {
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.name = "tc_clkevt",
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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/* Should be lower than at91rm9200's system timer */
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@ -330,39 +333,74 @@ static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_id
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writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
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}
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static int __init tcb_clksrc_init(void)
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{
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static char bootinfo[] __initdata
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= KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
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static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, };
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struct platform_device *pdev;
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struct atmel_tc *tc;
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static const struct of_device_id atmel_tcb_of_match[] = {
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{ .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, },
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{ .compatible = "atmel,at91sam9x5-tcb", .data = (void *)32, },
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{ /* sentinel */ }
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};
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static int __init tcb_clksrc_init(struct device_node *node)
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{
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struct atmel_tc tc;
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struct clk *t0_clk;
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const struct of_device_id *match;
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u64 (*tc_sched_clock)(void);
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u32 rate, divided_rate = 0;
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int best_divisor_idx = -1;
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int clk32k_divisor_idx = -1;
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int bits;
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int i;
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int ret;
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tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
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if (!tc) {
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pr_debug("can't alloc TC for clocksource\n");
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return -ENODEV;
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}
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tcaddr = tc->regs;
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pdev = tc->pdev;
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/* Protect against multiple calls */
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if (tcaddr)
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return 0;
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tc.regs = of_iomap(node->parent, 0);
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if (!tc.regs)
|
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return -ENXIO;
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t0_clk = of_clk_get_by_name(node->parent, "t0_clk");
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if (IS_ERR(t0_clk))
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return PTR_ERR(t0_clk);
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tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
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if (IS_ERR(tc.slow_clk))
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return PTR_ERR(tc.slow_clk);
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tc.clk[0] = t0_clk;
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tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk");
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if (IS_ERR(tc.clk[1]))
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tc.clk[1] = t0_clk;
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tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk");
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if (IS_ERR(tc.clk[2]))
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tc.clk[2] = t0_clk;
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tc.irq[2] = of_irq_get(node->parent, 2);
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if (tc.irq[2] <= 0) {
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tc.irq[2] = of_irq_get(node->parent, 0);
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if (tc.irq[2] <= 0)
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return -EINVAL;
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}
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match = of_match_node(atmel_tcb_of_match, node->parent);
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bits = (uintptr_t)match->data;
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for (i = 0; i < ARRAY_SIZE(tc.irq); i++)
|
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writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));
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t0_clk = tc->clk[0];
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ret = clk_prepare_enable(t0_clk);
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if (ret) {
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pr_debug("can't enable T0 clk\n");
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goto err_free_tc;
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return ret;
|
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}
|
||||
|
||||
/* How fast will we be counting? Pick something over 5 MHz. */
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rate = (u32) clk_get_rate(t0_clk);
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for (i = 0; i < 5; i++) {
|
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unsigned divisor = atmel_tc_divisors[i];
|
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for (i = 0; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
|
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unsigned divisor = atmel_tcb_divisors[i];
|
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unsigned tmp;
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|
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/* remember 32 KiHz clock for later */
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|
@ -381,27 +419,31 @@ static int __init tcb_clksrc_init(void)
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|||
best_divisor_idx = i;
|
||||
}
|
||||
|
||||
|
||||
printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
|
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divided_rate / 1000000,
|
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clksrc.name = kbasename(node->parent->full_name);
|
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clkevt.clkevt.name = kbasename(node->parent->full_name);
|
||||
pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000,
|
||||
((divided_rate % 1000000) + 500) / 1000);
|
||||
|
||||
if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
|
||||
tcaddr = tc.regs;
|
||||
|
||||
if (bits == 32) {
|
||||
/* use apropriate function to read 32 bit counter */
|
||||
clksrc.read = tc_get_cycles32;
|
||||
/* setup ony channel 0 */
|
||||
tcb_setup_single_chan(tc, best_divisor_idx);
|
||||
tcb_setup_single_chan(&tc, best_divisor_idx);
|
||||
tc_sched_clock = tc_sched_clock_read32;
|
||||
} else {
|
||||
/* tclib will give us three clocks no matter what the
|
||||
/* we have three clocks no matter what the
|
||||
* underlying platform supports.
|
||||
*/
|
||||
ret = clk_prepare_enable(tc->clk[1]);
|
||||
ret = clk_prepare_enable(tc.clk[1]);
|
||||
if (ret) {
|
||||
pr_debug("can't enable T1 clk\n");
|
||||
goto err_disable_t0;
|
||||
}
|
||||
/* setup both channel 0 & 1 */
|
||||
tcb_setup_dual_chan(tc, best_divisor_idx);
|
||||
tcb_setup_dual_chan(&tc, best_divisor_idx);
|
||||
tc_sched_clock = tc_sched_clock_read;
|
||||
}
|
||||
|
||||
/* and away we go! */
|
||||
|
|
@ -410,24 +452,26 @@ static int __init tcb_clksrc_init(void)
|
|||
goto err_disable_t1;
|
||||
|
||||
/* channel 2: periodic and oneshot timer support */
|
||||
ret = setup_clkevents(tc, clk32k_divisor_idx);
|
||||
ret = setup_clkevents(&tc, clk32k_divisor_idx);
|
||||
if (ret)
|
||||
goto err_unregister_clksrc;
|
||||
|
||||
sched_clock_register(tc_sched_clock, 32, divided_rate);
|
||||
|
||||
return 0;
|
||||
|
||||
err_unregister_clksrc:
|
||||
clocksource_unregister(&clksrc);
|
||||
|
||||
err_disable_t1:
|
||||
if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
|
||||
clk_disable_unprepare(tc->clk[1]);
|
||||
if (bits != 32)
|
||||
clk_disable_unprepare(tc.clk[1]);
|
||||
|
||||
err_disable_t0:
|
||||
clk_disable_unprepare(t0_clk);
|
||||
|
||||
err_free_tc:
|
||||
atmel_tc_free(tc);
|
||||
tcaddr = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
arch_initcall(tcb_clksrc_init);
|
||||
TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);
|
||||
|
|
@ -26,8 +26,8 @@
|
|||
#define MLB_TMR_TMCSR_CSL_DIV2 0
|
||||
#define MLB_TMR_DIV_CNT 2
|
||||
|
||||
#define MLB_TMR_SRC_CH (1)
|
||||
#define MLB_TMR_EVT_CH (0)
|
||||
#define MLB_TMR_SRC_CH 1
|
||||
#define MLB_TMR_EVT_CH 0
|
||||
|
||||
#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
|
||||
#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
|
||||
|
|
@ -43,6 +43,8 @@
|
|||
#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
|
||||
|
||||
#define MLB_TIMER_RATING 500
|
||||
#define MLB_TIMER_ONESHOT 0
|
||||
#define MLB_TIMER_PERIODIC 1
|
||||
|
||||
static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
|
|
@ -59,27 +61,53 @@ static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void mlb_evt_timer_start(struct timer_of *to, bool periodic)
|
||||
{
|
||||
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
|
||||
|
||||
val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
|
||||
if (periodic)
|
||||
val |= MLB_TMR_TMCSR_RELD;
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
}
|
||||
|
||||
static void mlb_evt_timer_stop(struct timer_of *to)
|
||||
{
|
||||
u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
|
||||
val &= ~MLB_TMR_TMCSR_CNTE;
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
}
|
||||
|
||||
static void mlb_evt_timer_register_count(struct timer_of *to, unsigned long cnt)
|
||||
{
|
||||
writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
|
||||
}
|
||||
|
||||
static int mlb_set_state_periodic(struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
|
||||
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
|
||||
writel_relaxed(to->of_clk.period, timer_of_base(to) +
|
||||
MLB_TMR_EVT_TMRLR1_OFS);
|
||||
val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
|
||||
MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
mlb_evt_timer_stop(to);
|
||||
mlb_evt_timer_register_count(to, to->of_clk.period);
|
||||
mlb_evt_timer_start(to, MLB_TIMER_PERIODIC);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mlb_set_state_oneshot(struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
|
||||
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
|
||||
mlb_evt_timer_stop(to);
|
||||
mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mlb_set_state_shutdown(struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
|
||||
mlb_evt_timer_stop(to);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -88,22 +116,21 @@ static int mlb_clkevt_next_event(unsigned long event,
|
|||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
|
||||
writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
|
||||
writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
|
||||
MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
|
||||
MLB_TMR_TMCSR_TRG, timer_of_base(to) +
|
||||
MLB_TMR_EVT_TMCSR_OFS);
|
||||
mlb_evt_timer_stop(to);
|
||||
mlb_evt_timer_register_count(to, event);
|
||||
mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mlb_config_clock_source(struct timer_of *to)
|
||||
{
|
||||
writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
|
||||
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
|
||||
u32 val = MLB_TMR_TMCSR_CSL_DIV2;
|
||||
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
|
||||
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
|
||||
writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
|
||||
writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
|
||||
MLB_TMR_SRC_TMCSR_OFS);
|
||||
val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG;
|
||||
writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -123,6 +150,7 @@ static struct timer_of to = {
|
|||
.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.set_state_oneshot = mlb_set_state_oneshot,
|
||||
.set_state_periodic = mlb_set_state_periodic,
|
||||
.set_state_shutdown = mlb_set_state_shutdown,
|
||||
.set_next_event = mlb_clkevt_next_event,
|
||||
},
|
||||
|
||||
|
|
|
|||
|
|
@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node)
|
|||
*/
|
||||
if (of_machine_is_compatible("allwinner,sun4i-a10") ||
|
||||
of_machine_is_compatible("allwinner,sun5i-a13") ||
|
||||
of_machine_is_compatible("allwinner,sun5i-a10s"))
|
||||
of_machine_is_compatible("allwinner,sun5i-a10s") ||
|
||||
of_machine_is_compatible("allwinner,suniv-f1c100s"))
|
||||
sched_clock_register(sun4i_timer_sched_read, 32,
|
||||
timer_of_rate(&to));
|
||||
|
||||
|
|
@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node)
|
|||
}
|
||||
TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
|
||||
sun4i_timer_init);
|
||||
TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
|
||||
sun4i_timer_init);
|
||||
|
|
|
|||
|
|
@ -60,9 +60,6 @@
|
|||
static u32 usec_config;
|
||||
static void __iomem *timer_reg_base;
|
||||
#ifdef CONFIG_ARM
|
||||
static void __iomem *rtc_base;
|
||||
static struct timespec64 persistent_ts;
|
||||
static u64 persistent_ms, last_persistent_ms;
|
||||
static struct delay_timer tegra_delay_timer;
|
||||
#endif
|
||||
|
||||
|
|
@ -199,40 +196,30 @@ static unsigned long tegra_delay_timer_read_counter_long(void)
|
|||
return readl(timer_reg_base + TIMERUS_CNTR_1US);
|
||||
}
|
||||
|
||||
static struct timer_of suspend_rtc_to = {
|
||||
.flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
|
||||
};
|
||||
|
||||
/*
|
||||
* tegra_rtc_read - Reads the Tegra RTC registers
|
||||
* Care must be taken that this funciton is not called while the
|
||||
* tegra_rtc driver could be executing to avoid race conditions
|
||||
* on the RTC shadow register
|
||||
*/
|
||||
static u64 tegra_rtc_read_ms(void)
|
||||
static u64 tegra_rtc_read_ms(struct clocksource *cs)
|
||||
{
|
||||
u32 ms = readl(rtc_base + RTC_MILLISECONDS);
|
||||
u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
|
||||
u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS);
|
||||
u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS);
|
||||
return (u64)s * MSEC_PER_SEC + ms;
|
||||
}
|
||||
|
||||
/*
|
||||
* tegra_read_persistent_clock64 - Return time from a persistent clock.
|
||||
*
|
||||
* Reads the time from a source which isn't disabled during PM, the
|
||||
* 32k sync timer. Convert the cycles elapsed since last read into
|
||||
* nsecs and adds to a monotonically increasing timespec64.
|
||||
* Care must be taken that this funciton is not called while the
|
||||
* tegra_rtc driver could be executing to avoid race conditions
|
||||
* on the RTC shadow register
|
||||
*/
|
||||
static void tegra_read_persistent_clock64(struct timespec64 *ts)
|
||||
{
|
||||
u64 delta;
|
||||
|
||||
last_persistent_ms = persistent_ms;
|
||||
persistent_ms = tegra_rtc_read_ms();
|
||||
delta = persistent_ms - last_persistent_ms;
|
||||
|
||||
timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
|
||||
*ts = persistent_ts;
|
||||
}
|
||||
static struct clocksource suspend_rtc_clocksource = {
|
||||
.name = "tegra_suspend_timer",
|
||||
.rating = 200,
|
||||
.read = tegra_rtc_read_ms,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
|
||||
};
|
||||
#endif
|
||||
|
||||
static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
|
||||
|
|
@ -385,25 +372,15 @@ static int __init tegra_init_timer(struct device_node *np)
|
|||
|
||||
static int __init tegra20_init_rtc(struct device_node *np)
|
||||
{
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
rtc_base = of_iomap(np, 0);
|
||||
if (!rtc_base) {
|
||||
pr_err("Can't map RTC registers\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
ret = timer_of_init(np, &suspend_rtc_to);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* rtc registers are used by read_persistent_clock, keep the rtc clock
|
||||
* enabled
|
||||
*/
|
||||
clk = of_clk_get(np, 0);
|
||||
if (IS_ERR(clk))
|
||||
pr_warn("Unable to get rtc-tegra clock\n");
|
||||
else
|
||||
clk_prepare_enable(clk);
|
||||
clocksource_register_hz(&suspend_rtc_clocksource, 1000);
|
||||
|
||||
return register_persistent_clock(tegra_read_persistent_clock64);
|
||||
return 0;
|
||||
}
|
||||
TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -59,30 +59,6 @@ config ATMEL_TCLIB
|
|||
blocks found on many Atmel processors. This facilitates using
|
||||
these blocks by different drivers despite processor differences.
|
||||
|
||||
config ATMEL_TCB_CLKSRC
|
||||
bool "TC Block Clocksource"
|
||||
depends on ATMEL_TCLIB
|
||||
default y
|
||||
help
|
||||
Select this to get a high precision clocksource based on a
|
||||
TC block with a 5+ MHz base clock rate. Two timer channels
|
||||
are combined to make a single 32-bit timer.
|
||||
|
||||
When GENERIC_CLOCKEVENTS is defined, the third timer channel
|
||||
may be used as a clock event device supporting oneshot mode
|
||||
(delays of up to two seconds) based on the 32 KiHz clock.
|
||||
|
||||
config ATMEL_TCB_CLKSRC_BLOCK
|
||||
int
|
||||
depends on ATMEL_TCB_CLKSRC
|
||||
default 0
|
||||
range 0 1
|
||||
help
|
||||
Some chips provide more than one TC block, so you have the
|
||||
choice of which one to use for the clock framework. The other
|
||||
TC can be used for other purposes, such as PWM generation and
|
||||
interval timing.
|
||||
|
||||
config DUMMY_IRQ
|
||||
tristate "Dummy IRQ handler"
|
||||
default n
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
#include <linux/atmel_tc.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
|
|
@ -10,6 +9,7 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/of.h>
|
||||
#include <soc/at91/atmel_tcb.h>
|
||||
|
||||
/*
|
||||
* This is a thin library to solve the problem of how to portably allocate
|
||||
|
|
@ -111,6 +111,9 @@ static int __init tc_probe(struct platform_device *pdev)
|
|||
struct resource *r;
|
||||
unsigned int i;
|
||||
|
||||
if (of_get_child_count(pdev->dev.of_node))
|
||||
return -EBUSY;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return -EINVAL;
|
||||
|
|
|
|||
|
|
@ -17,10 +17,10 @@
|
|||
#include <linux/ioport.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/atmel_tc.h>
|
||||
#include <linux/pwm.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <soc/at91/atmel_tcb.h>
|
||||
|
||||
#define NPWM 6
|
||||
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@
|
|||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef ATMEL_TC_H
|
||||
#define ATMEL_TC_H
|
||||
#ifndef __SOC_ATMEL_TCB_H
|
||||
#define __SOC_ATMEL_TCB_H
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/list.h>
|
||||
Loading…
Reference in New Issue
Block a user