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xtensa: enforce slab alignment to maximum register width

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XCHAL_DATA_WIDTH is the maximum register width, slab caches should be
aligned to this.

Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4
(wordsize) for now.  But the S6000 variant will raise this to 16.

Signed-off-by: Oskar Schirmer <os@emlix.com>
Signed-off-by: Johannes Weiner <jw@emlix.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Oskar Schirmer 2009-03-04 16:21:30 +01:00 committed by Chris Zankel
parent c947a585ab
commit a81cbd2da4
1 changed files with 2 additions and 0 deletions
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2
arch/xtensa/include/asm/processor.h
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@ -25,6 +25,8 @@
# error Linux requires the Xtensa Windowed Registers Option.
#endif
#define ARCH_SLAB_MINALIGN XCHAL_DATA_WIDTH
/*
* User space process size: 1 GB.
* Windowed call ABI requires caller and callee to be located within the same