Pull icc-cleanup into release branch
This commit is contained in:
Tony Luck
commit
ae02e964b6
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@ -10,7 +10,8 @@
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CPPFLAGS += -I$(srctree)/arch/ia64/sn/include
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obj-y += setup.o bte.o bte_error.o irq.o mca.o idle.o \
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huberror.o io_init.o iomv.o klconflib.o sn2/
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huberror.o io_init.o iomv.o klconflib.o pio_phys.o \
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sn2/
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obj-$(CONFIG_IA64_GENERIC) += machvec.o
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obj-$(CONFIG_SGI_TIOCX) += tiocx.o
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obj-$(CONFIG_IA64_SGI_SN_XP) += xp.o
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71
arch/ia64/sn/kernel/pio_phys.S
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71
arch/ia64/sn/kernel/pio_phys.S
Normal file
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@ -0,0 +1,71 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
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*
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* This file contains macros used to access MMR registers via
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* uncached physical addresses.
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* pio_phys_read_mmr - read an MMR
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* pio_phys_write_mmr - write an MMR
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* pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
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* Second MMR will be skipped if address is NULL
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*
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* Addresses passed to these routines should be uncached physical addresses
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* ie., 0x80000....
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*/
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#include <asm/asmmacro.h>
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#include <asm/page.h>
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GLOBAL_ENTRY(pio_phys_read_mmr)
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.prologue
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.regstk 1,0,0,0
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.body
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mov r2=psr
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rsm psr.i | psr.dt
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;;
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srlz.d
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ld8.acq r8=[r32]
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;;
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mov psr.l=r2;;
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srlz.d
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br.ret.sptk.many rp
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END(pio_phys_read_mmr)
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GLOBAL_ENTRY(pio_phys_write_mmr)
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.prologue
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.regstk 2,0,0,0
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.body
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mov r2=psr
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rsm psr.i | psr.dt
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;;
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srlz.d
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st8.rel [r32]=r33
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;;
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mov psr.l=r2;;
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srlz.d
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br.ret.sptk.many rp
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END(pio_phys_write_mmr)
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GLOBAL_ENTRY(pio_atomic_phys_write_mmrs)
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.prologue
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.regstk 4,0,0,0
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.body
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mov r2=psr
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cmp.ne p9,p0=r34,r0;
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rsm psr.i | psr.dt | psr.ic
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;;
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srlz.d
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st8.rel [r32]=r33
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(p9) st8.rel [r34]=r35
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;;
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mov psr.l=r2;;
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srlz.d
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br.ret.sptk.many rp
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END(pio_atomic_phys_write_mmrs)
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@ -5,113 +5,10 @@
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*
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* Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
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* Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
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* Copyright (C) 2005,2006 Hongjiu Lu <hongjiu.lu@intel.com>
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*
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*/
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#include <asm/types.h>
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void __lfetch(int lfhint, void *y);
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void __lfetch_excl(int lfhint, void *y);
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void __lfetch_fault(int lfhint, void *y);
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void __lfetch_fault_excl(int lfhint, void *y);
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/* In the following, whichFloatReg should be an integer from 0-127 */
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void __ldfs(const int whichFloatReg, void *src);
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void __ldfd(const int whichFloatReg, void *src);
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void __ldfe(const int whichFloatReg, void *src);
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void __ldf8(const int whichFloatReg, void *src);
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void __ldf_fill(const int whichFloatReg, void *src);
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void __stfs(void *dst, const int whichFloatReg);
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void __stfd(void *dst, const int whichFloatReg);
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void __stfe(void *dst, const int whichFloatReg);
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void __stf8(void *dst, const int whichFloatReg);
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void __stf_spill(void *dst, const int whichFloatReg);
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void __st1_rel(void *dst, const __s8 value);
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void __st2_rel(void *dst, const __s16 value);
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void __st4_rel(void *dst, const __s32 value);
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void __st8_rel(void *dst, const __s64 value);
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__u8 __ld1_acq(void *src);
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__u16 __ld2_acq(void *src);
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__u32 __ld4_acq(void *src);
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__u64 __ld8_acq(void *src);
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__u64 __fetchadd4_acq(__u32 *addend, const int increment);
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__u64 __fetchadd4_rel(__u32 *addend, const int increment);
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__u64 __fetchadd8_acq(__u64 *addend, const int increment);
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__u64 __fetchadd8_rel(__u64 *addend, const int increment);
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__u64 __getf_exp(double d);
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/* OS Related Itanium(R) Intrinsics */
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/* The names to use for whichReg and whichIndReg below come from
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the include file asm/ia64regs.h */
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__u64 __getIndReg(const int whichIndReg, __s64 index);
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__u64 __getReg(const int whichReg);
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void __setIndReg(const int whichIndReg, __s64 index, __u64 value);
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void __setReg(const int whichReg, __u64 value);
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void __mf(void);
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void __mfa(void);
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void __synci(void);
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void __itcd(__s64 pa);
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void __itci(__s64 pa);
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void __itrd(__s64 whichTransReg, __s64 pa);
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void __itri(__s64 whichTransReg, __s64 pa);
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void __ptce(__s64 va);
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void __ptcl(__s64 va, __s64 pagesz);
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void __ptcg(__s64 va, __s64 pagesz);
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void __ptcga(__s64 va, __s64 pagesz);
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void __ptri(__s64 va, __s64 pagesz);
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void __ptrd(__s64 va, __s64 pagesz);
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void __invala (void);
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void __invala_gr(const int whichGeneralReg /* 0-127 */ );
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void __invala_fr(const int whichFloatReg /* 0-127 */ );
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void __nop(const int);
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void __fc(__u64 *addr);
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void __sum(int mask);
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void __rum(int mask);
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void __ssm(int mask);
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void __rsm(int mask);
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__u64 __thash(__s64);
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__u64 __ttag(__s64);
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__s64 __tpa(__s64);
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/* Intrinsics for implementing get/put_user macros */
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void __st_user(const char *tableName, __u64 addr, char size, char relocType, __u64 val);
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void __ld_user(const char *tableName, __u64 addr, char size, char relocType);
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/* This intrinsic does not generate code, it creates a barrier across which
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* the compiler will not schedule data access instructions.
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*/
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void __memory_barrier(void);
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void __isrlz(void);
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void __dsrlz(void);
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__u64 _m64_mux1(__u64 a, const int n);
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__u64 __thash(__u64);
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/* Lock and Atomic Operation Related Intrinsics */
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__u64 _InterlockedExchange8(volatile __u8 *trgt, __u8 value);
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__u64 _InterlockedExchange16(volatile __u16 *trgt, __u16 value);
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__s64 _InterlockedExchange(volatile __u32 *trgt, __u32 value);
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__s64 _InterlockedExchange64(volatile __u64 *trgt, __u64 value);
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__u64 _InterlockedCompareExchange8_rel(volatile __u8 *dest, __u64 xchg, __u64 comp);
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__u64 _InterlockedCompareExchange8_acq(volatile __u8 *dest, __u64 xchg, __u64 comp);
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__u64 _InterlockedCompareExchange16_rel(volatile __u16 *dest, __u64 xchg, __u64 comp);
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__u64 _InterlockedCompareExchange16_acq(volatile __u16 *dest, __u64 xchg, __u64 comp);
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__u64 _InterlockedCompareExchange_rel(volatile __u32 *dest, __u64 xchg, __u64 comp);
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__u64 _InterlockedCompareExchange_acq(volatile __u32 *dest, __u64 xchg, __u64 comp);
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__u64 _InterlockedCompareExchange64_rel(volatile __u64 *dest, __u64 xchg, __u64 comp);
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__u64 _InterlockedCompareExchange64_acq(volatile __u64 *dest, __u64 xchg, __u64 comp);
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__s64 _m64_dep_mi(const int v, __s64 s, const int p, const int len);
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__s64 _m64_shrp(__s64 a, __s64 b, const int count);
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__s64 _m64_popcnt(__s64 a);
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#include <ia64intrin.h>
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#define ia64_barrier() __memory_barrier()
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@ -122,15 +19,16 @@ __s64 _m64_popcnt(__s64 a);
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#define ia64_getreg __getReg
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#define ia64_setreg __setReg
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#define ia64_hint(x)
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#define ia64_hint __hint
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#define ia64_hint_pause __hint_pause
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#define ia64_mux1_brcst 0
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#define ia64_mux1_mix 8
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#define ia64_mux1_shuf 9
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#define ia64_mux1_alt 10
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#define ia64_mux1_rev 11
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#define ia64_mux1_brcst _m64_mux1_brcst
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#define ia64_mux1_mix _m64_mux1_mix
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#define ia64_mux1_shuf _m64_mux1_shuf
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#define ia64_mux1_alt _m64_mux1_alt
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#define ia64_mux1_rev _m64_mux1_rev
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#define ia64_mux1 _m64_mux1
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#define ia64_mux1(x,v) _m_to_int64(_m64_mux1(_m_from_int64(x), (v)))
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#define ia64_popcnt _m64_popcnt
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#define ia64_getf_exp __getf_exp
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#define ia64_shrp _m64_shrp
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@ -158,7 +56,7 @@ __s64 _m64_popcnt(__s64 a);
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#define ia64_stf8 __stf8
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#define ia64_stf_spill __stf_spill
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#define ia64_mf __mf
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#define ia64_mf __mf
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#define ia64_mfa __mfa
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#define ia64_fetchadd4_acq __fetchadd4_acq
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@ -234,10 +132,10 @@ __s64 _m64_popcnt(__s64 a);
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/* Values for lfhint in __lfetch and __lfetch_fault */
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#define ia64_lfhint_none 0
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#define ia64_lfhint_nt1 1
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#define ia64_lfhint_nt2 2
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#define ia64_lfhint_nta 3
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#define ia64_lfhint_none __lfhint_none
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#define ia64_lfhint_nt1 __lfhint_nt1
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#define ia64_lfhint_nt2 __lfhint_nt2
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#define ia64_lfhint_nta __lfhint_nta
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#define ia64_lfetch __lfetch
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#define ia64_lfetch_excl __lfetch_excl
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@ -254,4 +152,6 @@ do { \
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} \
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} while (0)
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#define __builtin_trap() __break(0);
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#endif /* _ASM_IA64_INTEL_INTRIN_H */
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@ -3,15 +3,14 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002-2004 Silicon Graphics, Inc. All Rights Reserved.
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* Copyright (C) 2002-2006 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#ifndef _ASM_IA64_SN_RW_MMR_H
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#define _ASM_IA64_SN_RW_MMR_H
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/*
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* This file contains macros used to access MMR registers via
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* uncached physical addresses.
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* This file that access MMRs via uncached physical addresses.
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* pio_phys_read_mmr - read an MMR
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* pio_phys_write_mmr - write an MMR
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* pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
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@ -22,53 +21,8 @@
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*/
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extern inline long
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pio_phys_read_mmr(volatile long *mmr)
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{
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long val;
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asm volatile
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("mov r2=psr;;"
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"rsm psr.i | psr.dt;;"
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"srlz.i;;"
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"ld8.acq %0=[%1];;"
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"mov psr.l=r2;;"
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"srlz.i;;"
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: "=r"(val)
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: "r"(mmr)
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: "r2");
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return val;
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}
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extern inline void
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pio_phys_write_mmr(volatile long *mmr, long val)
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{
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asm volatile
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("mov r2=psr;;"
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"rsm psr.i | psr.dt;;"
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"srlz.i;;"
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"st8.rel [%0]=%1;;"
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"mov psr.l=r2;;"
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"srlz.i;;"
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:: "r"(mmr), "r"(val)
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: "r2", "memory");
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}
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extern inline void
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pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2)
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{
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asm volatile
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("mov r2=psr;;"
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"rsm psr.i | psr.dt | psr.ic;;"
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"cmp.ne p9,p0=%2,r0;"
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"srlz.i;;"
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"st8.rel [%0]=%1;"
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"(p9) st8.rel [%2]=%3;;"
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"mov psr.l=r2;;"
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"srlz.i;;"
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:: "r"(mmr1), "r"(val1), "r"(mmr2), "r"(val2)
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: "p9", "r2", "memory");
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}
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extern long pio_phys_read_mmr(volatile long *mmr);
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extern void pio_phys_write_mmr(volatile long *mmr, long val);
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extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2);
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#endif /* _ASM_IA64_SN_RW_MMR_H */
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