avr32: Clean up HMATRIX code
Introduce a few helper functions for HMATRIX configuration and clean up the register definitions. Also add definitions for the HMATRIX master and slave IDs on the AT32AP700x chips. Also make the definitions in hmatrix.h available to board code by moving it to <mach/hmatrix.h> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen
parent
a8d902db22
commit
b47eb4092f
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@ -1,4 +1,5 @@
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obj-y += pdc.o clock.o intc.o extint.o pio.o hsmc.o
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obj-y += hmatrix.o
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obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
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obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
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obj-$(CONFIG_PM) += pm.o
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@ -22,13 +22,13 @@
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#include <mach/at32ap700x.h>
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#include <mach/board.h>
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#include <mach/hmatrix.h>
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#include <mach/portmux.h>
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#include <mach/sram.h>
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#include <video/atmel_lcdc.h>
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#include "clock.h"
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#include "hmatrix.h"
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#include "pio.h"
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#include "pm.h"
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@ -725,7 +725,7 @@ static struct clk pico_clk = {
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* HMATRIX
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* -------------------------------------------------------------------- */
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static struct clk hmatrix_clk = {
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struct clk at32_hmatrix_clk = {
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.name = "hmatrix_clk",
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.parent = &pbb_clk,
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.mode = pbb_clk_mode,
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@ -733,12 +733,6 @@ static struct clk hmatrix_clk = {
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.index = 2,
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.users = 1,
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};
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#define HMATRIX_BASE ((void __iomem *)0xfff00800)
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#define hmatrix_readl(reg) \
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__raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
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#define hmatrix_writel(reg,value) \
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__raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
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/*
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* Set bits in the HMATRIX Special Function Register (SFR) used by the
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@ -748,13 +742,7 @@ static struct clk hmatrix_clk = {
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*/
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static inline void set_ebi_sfr_bits(u32 mask)
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{
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u32 sfr;
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clk_enable(&hmatrix_clk);
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sfr = hmatrix_readl(SFR4);
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sfr |= mask;
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hmatrix_writel(SFR4, sfr);
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clk_disable(&hmatrix_clk);
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hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
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}
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/* --------------------------------------------------------------------
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@ -1779,7 +1767,7 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
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return ret;
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select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
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set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
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hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
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break;
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case 5:
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ret = platform_device_add_resources(pdev,
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@ -1789,7 +1777,7 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
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return ret;
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select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
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set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
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hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
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break;
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default:
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return -EINVAL;
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@ -1905,7 +1893,7 @@ at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
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sizeof(struct atmel_nand_data)))
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goto fail;
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set_ebi_sfr_bits(HMATRIX_BIT(CS3A));
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hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
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if (data->enable_pin)
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at32_select_gpio(data->enable_pin,
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AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
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@ -2097,7 +2085,7 @@ struct clk *at32_clock_list[] = {
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&pbb_clk,
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&at32_pm_pclk,
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&at32_intc0_pclk,
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&hmatrix_clk,
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&at32_hmatrix_clk,
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&ebi_clk,
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&hramc_clk,
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&sdramc_clk,
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88
arch/avr32/mach-at32ap/hmatrix.c
Normal file
88
arch/avr32/mach-at32ap/hmatrix.c
Normal file
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@ -0,0 +1,88 @@
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/*
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* High-Speed Bus Matrix helper functions
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*
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* Copyright (C) 2008 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/chip.h>
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#include <mach/hmatrix.h>
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static inline void __hmatrix_write_reg(unsigned long offset, u32 value)
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{
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__raw_writel(value, (void __iomem __force *)(HMATRIX_BASE + offset));
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}
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static inline u32 __hmatrix_read_reg(unsigned long offset)
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{
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return __raw_readl((void __iomem __force *)(HMATRIX_BASE + offset));
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}
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/**
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* hmatrix_write_reg - write HMATRIX configuration register
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* @offset: register offset
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* @value: value to be written to the register at @offset
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*/
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void hmatrix_write_reg(unsigned long offset, u32 value)
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{
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clk_enable(&at32_hmatrix_clk);
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__hmatrix_write_reg(offset, value);
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__hmatrix_read_reg(offset);
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clk_disable(&at32_hmatrix_clk);
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}
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/**
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* hmatrix_read_reg - read HMATRIX configuration register
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* @offset: register offset
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*
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* Returns the value of the register at @offset.
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*/
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u32 hmatrix_read_reg(unsigned long offset)
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{
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u32 value;
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clk_enable(&at32_hmatrix_clk);
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value = __hmatrix_read_reg(offset);
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clk_disable(&at32_hmatrix_clk);
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return value;
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}
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/**
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* hmatrix_sfr_set_bits - set bits in a slave's Special Function Register
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* @slave_id: operate on the SFR belonging to this slave
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* @mask: mask of bits to be set in the SFR
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*/
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void hmatrix_sfr_set_bits(unsigned int slave_id, u32 mask)
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{
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u32 value;
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clk_enable(&at32_hmatrix_clk);
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value = __hmatrix_read_reg(HMATRIX_SFR(slave_id));
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value |= mask;
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__hmatrix_write_reg(HMATRIX_SFR(slave_id), value);
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__hmatrix_read_reg(HMATRIX_SFR(slave_id));
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clk_disable(&at32_hmatrix_clk);
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}
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/**
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* hmatrix_sfr_set_bits - clear bits in a slave's Special Function Register
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* @slave_id: operate on the SFR belonging to this slave
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* @mask: mask of bits to be cleared in the SFR
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*/
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void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask)
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{
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u32 value;
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clk_enable(&at32_hmatrix_clk);
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value = __hmatrix_read_reg(HMATRIX_SFR(slave_id));
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value &= ~mask;
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__hmatrix_write_reg(HMATRIX_SFR(slave_id), value);
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__hmatrix_read_reg(HMATRIX_SFR(slave_id));
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clk_disable(&at32_hmatrix_clk);
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}
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@ -1,182 +0,0 @@
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/*
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* Register definitions for High-Speed Bus Matrix
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*/
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#ifndef __HMATRIX_H
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#define __HMATRIX_H
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/* HMATRIX register offsets */
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#define HMATRIX_MCFG0 0x0000
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#define HMATRIX_MCFG1 0x0004
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#define HMATRIX_MCFG2 0x0008
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#define HMATRIX_MCFG3 0x000c
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#define HMATRIX_MCFG4 0x0010
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#define HMATRIX_MCFG5 0x0014
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#define HMATRIX_MCFG6 0x0018
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#define HMATRIX_MCFG7 0x001c
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#define HMATRIX_MCFG8 0x0020
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#define HMATRIX_MCFG9 0x0024
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#define HMATRIX_MCFG10 0x0028
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#define HMATRIX_MCFG11 0x002c
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#define HMATRIX_MCFG12 0x0030
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#define HMATRIX_MCFG13 0x0034
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#define HMATRIX_MCFG14 0x0038
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#define HMATRIX_MCFG15 0x003c
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#define HMATRIX_SCFG0 0x0040
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#define HMATRIX_SCFG1 0x0044
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#define HMATRIX_SCFG2 0x0048
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#define HMATRIX_SCFG3 0x004c
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#define HMATRIX_SCFG4 0x0050
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#define HMATRIX_SCFG5 0x0054
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#define HMATRIX_SCFG6 0x0058
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#define HMATRIX_SCFG7 0x005c
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#define HMATRIX_SCFG8 0x0060
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#define HMATRIX_SCFG9 0x0064
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#define HMATRIX_SCFG10 0x0068
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#define HMATRIX_SCFG11 0x006c
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#define HMATRIX_SCFG12 0x0070
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#define HMATRIX_SCFG13 0x0074
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#define HMATRIX_SCFG14 0x0078
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#define HMATRIX_SCFG15 0x007c
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#define HMATRIX_PRAS0 0x0080
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#define HMATRIX_PRBS0 0x0084
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#define HMATRIX_PRAS1 0x0088
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#define HMATRIX_PRBS1 0x008c
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#define HMATRIX_PRAS2 0x0090
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#define HMATRIX_PRBS2 0x0094
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#define HMATRIX_PRAS3 0x0098
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#define HMATRIX_PRBS3 0x009c
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#define HMATRIX_PRAS4 0x00a0
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#define HMATRIX_PRBS4 0x00a4
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#define HMATRIX_PRAS5 0x00a8
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#define HMATRIX_PRBS5 0x00ac
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#define HMATRIX_PRAS6 0x00b0
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#define HMATRIX_PRBS6 0x00b4
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#define HMATRIX_PRAS7 0x00b8
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#define HMATRIX_PRBS7 0x00bc
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#define HMATRIX_PRAS8 0x00c0
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#define HMATRIX_PRBS8 0x00c4
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#define HMATRIX_PRAS9 0x00c8
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#define HMATRIX_PRBS9 0x00cc
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#define HMATRIX_PRAS10 0x00d0
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#define HMATRIX_PRBS10 0x00d4
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#define HMATRIX_PRAS11 0x00d8
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#define HMATRIX_PRBS11 0x00dc
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#define HMATRIX_PRAS12 0x00e0
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#define HMATRIX_PRBS12 0x00e4
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#define HMATRIX_PRAS13 0x00e8
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#define HMATRIX_PRBS13 0x00ec
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#define HMATRIX_PRAS14 0x00f0
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#define HMATRIX_PRBS14 0x00f4
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#define HMATRIX_PRAS15 0x00f8
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#define HMATRIX_PRBS15 0x00fc
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#define HMATRIX_MRCR 0x0100
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#define HMATRIX_SFR0 0x0110
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#define HMATRIX_SFR1 0x0114
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#define HMATRIX_SFR2 0x0118
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#define HMATRIX_SFR3 0x011c
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#define HMATRIX_SFR4 0x0120
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#define HMATRIX_SFR5 0x0124
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#define HMATRIX_SFR6 0x0128
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#define HMATRIX_SFR7 0x012c
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#define HMATRIX_SFR8 0x0130
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#define HMATRIX_SFR9 0x0134
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#define HMATRIX_SFR10 0x0138
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#define HMATRIX_SFR11 0x013c
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#define HMATRIX_SFR12 0x0140
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#define HMATRIX_SFR13 0x0144
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#define HMATRIX_SFR14 0x0148
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#define HMATRIX_SFR15 0x014c
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/* Bitfields in MCFGx */
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#define HMATRIX_ULBT_OFFSET 0
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#define HMATRIX_ULBT_SIZE 3
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/* Bitfields in SCFGx */
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#define HMATRIX_SLOT_CYCLE_OFFSET 0
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#define HMATRIX_SLOT_CYCLE_SIZE 8
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#define HMATRIX_DEFMSTR_TYPE_OFFSET 16
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#define HMATRIX_DEFMSTR_TYPE_SIZE 2
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#define HMATRIX_FIXED_DEFMSTR_OFFSET 18
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#define HMATRIX_FIXED_DEFMSTR_SIZE 4
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#define HMATRIX_ARBT_OFFSET 24
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#define HMATRIX_ARBT_SIZE 2
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/* Bitfields in PRASx */
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#define HMATRIX_M0PR_OFFSET 0
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#define HMATRIX_M0PR_SIZE 4
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#define HMATRIX_M1PR_OFFSET 4
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#define HMATRIX_M1PR_SIZE 4
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#define HMATRIX_M2PR_OFFSET 8
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#define HMATRIX_M2PR_SIZE 4
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#define HMATRIX_M3PR_OFFSET 12
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#define HMATRIX_M3PR_SIZE 4
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#define HMATRIX_M4PR_OFFSET 16
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#define HMATRIX_M4PR_SIZE 4
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#define HMATRIX_M5PR_OFFSET 20
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#define HMATRIX_M5PR_SIZE 4
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#define HMATRIX_M6PR_OFFSET 24
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#define HMATRIX_M6PR_SIZE 4
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#define HMATRIX_M7PR_OFFSET 28
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#define HMATRIX_M7PR_SIZE 4
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/* Bitfields in PRBSx */
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#define HMATRIX_M8PR_OFFSET 0
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#define HMATRIX_M8PR_SIZE 4
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#define HMATRIX_M9PR_OFFSET 4
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#define HMATRIX_M9PR_SIZE 4
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#define HMATRIX_M10PR_OFFSET 8
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#define HMATRIX_M10PR_SIZE 4
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#define HMATRIX_M11PR_OFFSET 12
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#define HMATRIX_M11PR_SIZE 4
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#define HMATRIX_M12PR_OFFSET 16
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#define HMATRIX_M12PR_SIZE 4
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#define HMATRIX_M13PR_OFFSET 20
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#define HMATRIX_M13PR_SIZE 4
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#define HMATRIX_M14PR_OFFSET 24
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#define HMATRIX_M14PR_SIZE 4
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#define HMATRIX_M15PR_OFFSET 28
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#define HMATRIX_M15PR_SIZE 4
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/* Bitfields in SFR4 */
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#define HMATRIX_CS1A_OFFSET 1
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#define HMATRIX_CS1A_SIZE 1
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#define HMATRIX_CS3A_OFFSET 3
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#define HMATRIX_CS3A_SIZE 1
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#define HMATRIX_CS4A_OFFSET 4
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#define HMATRIX_CS4A_SIZE 1
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#define HMATRIX_CS5A_OFFSET 5
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#define HMATRIX_CS5A_SIZE 1
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#define HMATRIX_DBPUC_OFFSET 8
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#define HMATRIX_DBPUC_SIZE 1
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/* Constants for ULBT */
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#define HMATRIX_ULBT_INFINITE 0
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#define HMATRIX_ULBT_SINGLE 1
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#define HMATRIX_ULBT_FOUR_BEAT 2
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#define HMATRIX_ULBT_EIGHT_BEAT 3
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#define HMATRIX_ULBT_SIXTEEN_BEAT 4
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/* Constants for DEFMSTR_TYPE */
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#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT 0
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#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT 1
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#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT 2
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/* Constants for ARBT */
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#define HMATRIX_ARBT_ROUND_ROBIN 0
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#define HMATRIX_ARBT_FIXED_PRIORITY 1
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/* Bit manipulation macros */
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#define HMATRIX_BIT(name) \
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(1 << HMATRIX_##name##_OFFSET)
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#define HMATRIX_BF(name,value) \
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(((value) & ((1 << HMATRIX_##name##_SIZE) - 1)) \
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<< HMATRIX_##name##_OFFSET)
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#define HMATRIX_BFEXT(name,value) \
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(((value) >> HMATRIX_##name##_OFFSET) \
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& ((1 << HMATRIX_##name##_SIZE) - 1))
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#define HMATRIX_BFINS(name,value,old) \
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(((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1) \
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<< HMATRIX_##name##_OFFSET)) \
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| HMATRIX_BF(name,value))
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#endif /* __HMATRIX_H */
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@ -46,6 +46,35 @@
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#define DMAC_DMAREQ_2 9
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#define DMAC_DMAREQ_3 10
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/* HSB master IDs */
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#define HMATRIX_MASTER_CPU_DCACHE 0
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#define HMATRIX_MASTER_CPU_ICACHE 1
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#define HMATRIX_MASTER_PDC 2
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#define HMATRIX_MASTER_ISI 3
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#define HMATRIX_MASTER_USBA 4
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#define HMATRIX_MASTER_LCDC 5
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#define HMATRIX_MASTER_MACB0 6
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#define HMATRIX_MASTER_MACB1 7
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#define HMATRIX_MASTER_DMACA_M0 8
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#define HMATRIX_MASTER_DMACA_M1 9
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/* HSB slave IDs */
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#define HMATRIX_SLAVE_SRAM0 0
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#define HMATRIX_SLAVE_SRAM1 1
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#define HMATRIX_SLAVE_PBA 2
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#define HMATRIX_SLAVE_PBB 3
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#define HMATRIX_SLAVE_EBI 4
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#define HMATRIX_SLAVE_USBA 5
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#define HMATRIX_SLAVE_LCDC 6
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#define HMATRIX_SLAVE_DMACA 7
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/* Bits in HMATRIX SFR4 (EBI) */
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#define HMATRIX_EBI_SDRAM_ENABLE (1 << 1)
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#define HMATRIX_EBI_NAND_ENABLE (1 << 3)
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||||
#define HMATRIX_EBI_CF0_ENABLE (1 << 4)
|
||||
#define HMATRIX_EBI_CF1_ENABLE (1 << 5)
|
||||
#define HMATRIX_EBI_PULLUP_DISABLE (1 << 8)
|
||||
|
||||
/*
|
||||
* Base addresses of controllers that may be accessed early by
|
||||
* platform code.
|
||||
|
|
|
|||
55
arch/avr32/mach-at32ap/include/mach/hmatrix.h
Normal file
55
arch/avr32/mach-at32ap/include/mach/hmatrix.h
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* High-Speed Bus Matrix configuration registers
|
||||
*
|
||||
* Copyright (C) 2008 Atmel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __HMATRIX_H
|
||||
#define __HMATRIX_H
|
||||
|
||||
extern struct clk at32_hmatrix_clk;
|
||||
|
||||
void hmatrix_write_reg(unsigned long offset, u32 value);
|
||||
u32 hmatrix_read_reg(unsigned long offset);
|
||||
|
||||
void hmatrix_sfr_set_bits(unsigned int slave_id, u32 mask);
|
||||
void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
|
||||
|
||||
/* Master Configuration register */
|
||||
#define HMATRIX_MCFG(m) (0x0000 + 4 * (m))
|
||||
/* Undefined length burst limit */
|
||||
# define HMATRIX_MCFG_ULBT_INFINITE 0 /* Infinite length */
|
||||
# define HMATRIX_MCFG_ULBT_SINGLE 1 /* Single Access */
|
||||
# define HMATRIX_MCFG_ULBT_FOUR_BEAT 2 /* Four beat */
|
||||
# define HMATRIX_MCFG_ULBT_EIGHT_BEAT 3 /* Eight beat */
|
||||
# define HMATRIX_MCFG_ULBT_SIXTEEN_BEAT 4 /* Sixteen beat */
|
||||
|
||||
/* Slave Configuration register */
|
||||
#define HMATRIX_SCFG(s) (0x0040 + 4 * (s))
|
||||
# define HMATRIX_SCFG_SLOT_CYCLE(x) ((x) << 0) /* Max burst cycles */
|
||||
# define HMATRIX_SCFG_DEFMSTR_NONE ( 0 << 16) /* No default master */
|
||||
# define HMATRIX_SCFG_DEFMSTR_LAST ( 1 << 16) /* Last def master */
|
||||
# define HMATRIX_SCFG_DEFMSTR_FIXED ( 2 << 16) /* Fixed def master */
|
||||
# define HMATRIX_SCFG_FIXED_DEFMSTR(m) ((m) << 18) /* Fixed master ID */
|
||||
# define HMATRIX_SCFG_ARBT_ROUND_ROBIN ( 0 << 24) /* RR arbitration */
|
||||
# define HMATRIX_SCFG_ARBT_FIXED_PRIO ( 1 << 24) /* Fixed priority */
|
||||
|
||||
/* Slave Priority register A (master 0..7) */
|
||||
#define HMATRIX_PRAS(s) (0x0080 + 8 * (s))
|
||||
# define HMATRIX_PRAS_PRIO(m, p) ((p) << ((m) * 4))
|
||||
|
||||
/* Slave Priority register A (master 8..15) */
|
||||
#define HMATRIX_PRBS(s) (0x0084 + 8 * (s))
|
||||
# define HMATRIX_PRBS_PRIO(m, p) ((p) << (((m) - 8) * 4))
|
||||
|
||||
/* Master Remap Control Register */
|
||||
#define HMATRIX_MRCR 0x0100
|
||||
# define HMATRIX_MRCR_REMAP(m) ( 1 << (m)) /* Remap master m */
|
||||
|
||||
/* Special Function Register. Bit definitions are chip-specific */
|
||||
#define HMATRIX_SFR(s) (0x0110 + 4 * (s))
|
||||
|
||||
#endif /* __HMATRIX_H */
|
||||
Loading…
Reference in New Issue
Block a user