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sh: SH7780 Solution Engine board support.

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This adds support for the SH7780-based Solution Engine reference board.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.zh@hitachi.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Nobuhiro Iwamatsu 2007-03-29 00:07:35 +09:00 committed by Paul Mundt
parent cd6c7ea234
commit b75762302e
10 changed files with 1686 additions and 8 deletions
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8
arch/sh/Kconfig
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@ -99,6 +99,14 @@ config SH_7751_SOLUTION_ENGINE
help
Select 7751 SolutionEngine if configuring for a Hitachi SH7751
evaluation board.
config SH_7780_SOLUTION_ENGINE
bool "SolutionEngine7780"
select SOLUTION_ENGINE
select CPU_SUBTYPE_SH7780
help
Select 7780 SolutionEngine if configuring for a Renesas SH7780
evaluation board.
config SH_7300_SOLUTION_ENGINE
bool "SolutionEngine7300"

1
arch/sh/Makefile
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@ -89,6 +89,7 @@ core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
# Boards
machdir-$(CONFIG_SH_SOLUTION_ENGINE) := se/770x
machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) := se/7751
machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE) := se/7780
machdir-$(CONFIG_SH_7300_SOLUTION_ENGINE) := se/7300
machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE) := se/7343
machdir-$(CONFIG_SH_73180_SOLUTION_ENGINE) := se/73180

10
arch/sh/boards/se/7780/Makefile Normal file
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@ -0,0 +1,10 @@
#
# Makefile for the HITACHI UL SolutionEngine 7780 specific parts of the kernel
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
#
obj-y := setup.o irq.o

89
arch/sh/boards/se/7780/irq.c Normal file
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@ -0,0 +1,89 @@
/*
* linux/arch/sh/boards/se/7780/irq.c
*
* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7780 Support.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/se7780.h>
#define INTC_INTMSK0 0xFFD00044
#define INTC_INTMSKCLR0 0xFFD00064
static void disable_se7780_irq(unsigned int irq)
{
struct intc2_data *p = get_irq_chip_data(irq);
ctrl_outl(1 << p->msk_shift, INTC_INTMSK0 + p->msk_offset);
}
static void enable_se7780_irq(unsigned int irq)
{
struct intc2_data *p = get_irq_chip_data(irq);
ctrl_outl(1 << p->msk_shift, INTC_INTMSKCLR0 + p->msk_offset);
}
static struct irq_chip se7780_irq_chip __read_mostly = {
.name = "SE7780",
.mask = disable_se7780_irq,
.unmask = enable_se7780_irq,
.mask_ack = disable_se7780_irq,
};
static struct intc2_data intc2_irq_table[] = {
{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT1 */
{ 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT2 */
{ 6, 0, 29, 0, 29, 3 }, /* daughter board EXTINT3 */
{ 8, 0, 28, 0, 28, 3 }, /* SMC 91C111 (LAN) */
{ 10, 0, 27, 0, 27, 3 }, /* daughter board EXTINT4 */
{ 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT5 */
{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT6 */
{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT7 */
{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT8 */
{ 0 , 0, 24, 0, 24, 3 }, /* SM501 */
};
/*
* Initialize IRQ setting
*/
void __init init_se7780_IRQ(void)
{
int i ;
/* enable all interrupt at FPGA */
ctrl_outw(0, FPGA_INTMSK1);
/* mask SM501 interrupt */
ctrl_outw((ctrl_inw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
/* enable all interrupt at FPGA */
ctrl_outw(0, FPGA_INTMSK2);
/* set FPGA INTSEL register */
/* FPGA + 0x06 */
ctrl_outw( ((IRQPIN_SM501 << IRQPOS_SM501) |
(IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
/* FPGA + 0x08 */
ctrl_outw(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
(IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
(IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
(IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
/* FPGA + 0x0A */
ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++) {
disable_irq_nosync(intc2_irq_table[i].irq);
set_irq_chip_and_handler_name( intc2_irq_table[i].irq, &se7780_irq_chip,
handle_level_irq, "level");
set_irq_chip_data( intc2_irq_table[i].irq, &intc2_irq_table[i] );
disable_se7780_irq(intc2_irq_table[i].irq);
}
}

122
arch/sh/boards/se/7780/setup.c Normal file
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@ -0,0 +1,122 @@
/*
* linux/arch/sh/boards/se/7780/setup.c
*
* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7780 Support.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/machvec.h>
#include <asm/se7780.h>
#include <asm/io.h>
/* Heartbeat */
static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
static struct resource heartbeat_resources[] = {
[0] = {
.start = PA_LED,
.end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device heartbeat_device = {
.name = "heartbeat",
.id = -1,
.dev = {
.platform_data = heartbeat_bit_pos,
},
.num_resources = ARRAY_SIZE(heartbeat_resources),
.resource = heartbeat_resources,
};
/* SMC91x */
static struct resource smc91x_eth_resources[] = {
[0] = {
.name = "smc91x-regs" ,
.start = PA_LAN + 0x300,
.end = PA_LAN + 0x300 + 0x10 ,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = SMC_IRQ,
.end = SMC_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_eth_device = {
.name = "smc91x",
.id = 0,
.dev = {
.dma_mask = NULL, /* don't use dma */
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(smc91x_eth_resources),
.resource = smc91x_eth_resources,
};
static struct platform_device *se7780_devices[] __initdata = {
&heartbeat_device,
&smc91x_eth_device,
};
static int __init se7780_devices_setup(void)
{
return platform_add_devices(se7780_devices,
ARRAY_SIZE(se7780_devices));
}
device_initcall(se7780_devices_setup);
#define GPIO_PHCR 0xFFEA000E
#define GPIO_PMSELR 0xFFEA0080
#define GPIO_PECR 0xFFEA0008
static void __init se7780_setup(char **cmdline_p)
{
/* "SH-Linux" on LED Display */
ctrl_outw( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
ctrl_outw( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
ctrl_outw( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
ctrl_outw( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
ctrl_outw( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
ctrl_outw( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
ctrl_outw( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
ctrl_outw( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n");
/*
* PCI REQ/GNT setting
* REQ0/GNT0 -> USB
* REQ1/GNT1 -> PC Card
* REQ2/GNT2 -> Serial ATA
* REQ3/GNT3 -> PCI slot
*/
ctrl_outw(0x0213, FPGA_REQSEL);
/* GPIO setting */
ctrl_outw(0x0000, GPIO_PECR);
ctrl_outw(ctrl_inw(GPIO_PHCR)&0xfff3, GPIO_PHCR);
ctrl_outw(0x0c00, GPIO_PMSELR);
/* iVDR Power ON */
ctrl_outw(0x0001, FPGA_IVDRPW);
}
/*
* The Machine Vector
*/
struct sh_machine_vector mv_se7780 __initmv = {
.mv_name = "Solution Engine 7780" ,
.mv_setup = se7780_setup ,
.mv_nr_irqs = 111 ,
.mv_init_irq = init_se7780_IRQ,
};
ALIAS_MV(se7780)

1309
arch/sh/configs/se7780_defconfig Normal file
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File diff suppressed because it is too large Load Diff

30
arch/sh/drivers/pci/pci-sh7780.c
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@ -72,12 +72,27 @@ static int __init sh7780_pci_init(void)
}
/* Setup the INTC */
ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */
ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */
ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */
ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */
ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */
if (mach_is_7780se()) {
/* ICR0: IRL=use separately */
ctrl_outl(0x00C00020, INTC_ICR0);
/* ICR1: detect low level(for 2ndcut) */
ctrl_outl(0xAAAA0000, INTC_ICR1);
/* INTPRI: priority=3(all) */
ctrl_outl(0x33333333, INTC_INTPRI);
} else {
/* INTC SH-4 Mode */
ctrl_outl(0x00200000, INTC_ICR0);
/* enable PCIINTA - PCIINTD */
ctrl_outl(0x00078000, INTC_INT2MSKCR);
/* disable IRL4-7 Interrupt */
ctrl_outl(0x40000000, INTC_INTMSK1);
/* disable IRL4-7 Interrupt */
ctrl_outl(0x0000fffe, INTC_INTMSK2);
/* enable IRL0-3 Interrupt */
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
/* enable IRL0-3 Interrupt */
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
}
if ((ret = sh4_pci_check_direct()) != 0)
return ret;
@ -147,9 +162,8 @@ int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
* DMA interrupts...
*/
#ifdef CONFIG_SH_HIGHLANDER
/* Apply any last-minute PCIC fixups */
pci_fixup_pcic();
#endif
/* SH7780 init done, set central function init complete */
/* use round robin mode to stop a device starving/overruning */

16
arch/sh/drivers/pci/pci-sh7780.h
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@ -66,6 +66,22 @@
#define SH7780_PCIPMCSR_BSE 0x046
#define SH7780_PCICDD 0x047
#define SH7780_PCICR 0x100 /* PCI Control Register */
#define SH7780_PCILSR 0x104 /* PCI Local Space Register0 */
#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
#define SH7780_PCIAIR 0x11C /* Error Address Register */
#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
#define SH7780_PCIMBR0 0x1E0
#define SH7780_PCIMBMR0 0x1E4
#define SH7780_PCIMBR2 0x1F0

1
arch/sh/tools/mach-types
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@ -9,6 +9,7 @@ SE SH_SOLUTION_ENGINE
7751SE SH_7751_SOLUTION_ENGINE
7300SE SH_7300_SOLUTION_ENGINE
7343SE SH_7343_SOLUTION_ENGINE
7780SE SH_7780_SOLUTION_ENGINE
73180SE SH_73180_SOLUTION_ENGINE
7751SYSTEMH SH_7751_SYSTEMH
HP6XX SH_HP6XX

108
include/asm-sh/se7780.h Normal file
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@ -0,0 +1,108 @@
#ifndef __ASM_SH_SE7780_H
#define __ASM_SH_SE7780_H
/*
* linux/include/asm-sh/se7780.h
*
* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
*
* Hitachi UL SolutionEngine 7780 Support.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <asm/addrspace.h>
/* Box specific addresses. */
#define SE_AREA0_WIDTH 4 /* Area0: 32bit */
#define PA_ROM 0xa0000000 /* EPROM */
#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
#define PA_FROM 0xa1000000 /* Flash-ROM */
#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
#define PA_EXT1 0xa4000000
#define PA_EXT1_SIZE 0x04000000
#define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */
#define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */
#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
#define PA_SDRAM_SIZE 0x08000000
#define PA_EXT4 0xb0000000
#define PA_EXT4_SIZE 0x04000000
#define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */
#define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */
#define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */
#define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */
#define DISP_CHAR_RAM (7 << 3)
#define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0)
#define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1)
#define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2)
#define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3)
#define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4)
#define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5)
#define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6)
#define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7)
#define DISP_UDC_RAM (5 << 3)
#define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
/* FPGA register address and bit */
#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */
#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */
#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */
#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */
#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */
#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */
#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */
#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */
#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */
#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */
#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */
#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */
#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */
#define PA_LED FPGA_DBG_LED
#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */
#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */
#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */
/* FPGA INTSEL position */
/* INTSEL1 */
#define IRQPOS_SMC91CX (0 * 4)
#define IRQPOS_SM501 (1 * 4)
/* INTSEL2 */
#define IRQPOS_EXTINT1 (0 * 4)
#define IRQPOS_EXTINT2 (1 * 4)
#define IRQPOS_EXTINT3 (2 * 4)
#define IRQPOS_EXTINT4 (3 * 4)
/* INTSEL3 */
#define IRQPOS_PCCPW (0 * 4)
/* IDE interrupt */
#define IRQ_IDE0 67 /* iVDR */
/* SMC interrupt */
#define SMC_IRQ 8
/* SM501 interrupt */
#define SM501_IRQ 0
/* interrupt pin */
#define IRQPIN_EXTINT1 0 /* IRQ0 pin */
#define IRQPIN_EXTINT2 1 /* IRQ1 pin */
#define IRQPIN_EXTINT3 2 /* IRQ2 pin */
#define IRQPIN_SMC91CX 3 /* IRQ3 pin */
#define IRQPIN_EXTINT4 4 /* IRQ4 pin */
#define IRQPIN_PCC0 5 /* IRQ5 pin */
#define IRQPIN_PCC2 6 /* IRQ6 pin */
#define IRQPIN_SM501 7 /* IRQ7 pin */
#define IRQPIN_PCCPW 7 /* IRQ7 pin */
/* arch/sh/boards/se/7780/irq.c */
void init_se7780_IRQ(void);
#define __IO_PREFIX se7780
#include <asm/io_generic.h>
#endif /* __ASM_SH_SE7780_H */