[PATCH] tgafb: support the DirectColor visual
The 32-plane variations of the TGA use the Bt463 RAMDAC and are therefore DirectColor rather than TrueColor adapters. This is a set of changes to implement the necessary bits to support this model. A couple of fixes to fix accesses to the RAMDAC are included as a side-effect. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Simmons <jsimmons@infradead.org> Cc: "Antonino A. Daplas" <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -99,6 +99,12 @@ tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
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if (var->bits_per_pixel != 32)
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return -EINVAL;
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}
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var->red.length = var->green.length = var->blue.length = 8;
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if (var->bits_per_pixel == 32) {
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var->red.offset = 16;
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var->green.offset = 8;
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var->blue.offset = 0;
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}
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if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
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return -EINVAL;
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@ -152,7 +158,7 @@ tgafb_set_par(struct fb_info *info)
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struct tga_par *par = (struct tga_par *) info->par;
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u32 htimings, vtimings, pll_freq;
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u8 tga_type;
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int i, j;
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int i;
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/* Encode video timings. */
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htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
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@ -227,8 +233,10 @@ tgafb_set_par(struct fb_info *info)
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BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
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TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
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#ifdef CONFIG_HW_CONSOLE
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for (i = 0; i < 16; i++) {
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j = color_table[i];
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int j = color_table[i];
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TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
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@ -236,14 +244,17 @@ tgafb_set_par(struct fb_info *info)
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TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
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TGA_RAMDAC_REG);
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}
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for (i = 0; i < 240*3; i += 4) {
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TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
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for (i = 0; i < 240 * 3; i += 4) {
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#else
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for (i = 0; i < 256 * 3; i += 4) {
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#endif
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TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
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TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
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TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
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TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
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TGA_RAMDAC_REG);
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}
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@ -267,26 +278,24 @@ tgafb_set_par(struct fb_info *info)
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/* Fill the palette. */
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BT463_LOAD_ADDR(par, 0x0000);
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TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
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#ifdef CONFIG_HW_CONSOLE
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for (i = 0; i < 16; i++) {
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j = color_table[i];
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TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
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TGA_RAMDAC_REG);
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int j = color_table[i];
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TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
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}
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for (i = 0; i < 512*3; i += 4) {
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TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
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TGA_RAMDAC_REG);
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for (i = 0; i < 512 * 3; i += 4) {
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#else
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for (i = 0; i < 528 * 3; i += 4) {
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#endif
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TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
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}
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/* Fill window type table after start of vertical retrace. */
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@ -299,15 +308,12 @@ tgafb_set_par(struct fb_info *info)
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TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
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BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
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TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
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TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
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for (i = 0; i < 16; i++) {
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TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
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TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
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}
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}
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@ -435,9 +441,16 @@ tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
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TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
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} else if (regno < 16) {
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u32 value = (red << 16) | (green << 8) | blue;
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((u32 *)info->pseudo_palette)[regno] = value;
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} else {
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if (regno < 16) {
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u32 value = (regno << 16) | (regno << 8) | regno;
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((u32 *)info->pseudo_palette)[regno] = value;
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}
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BT463_LOAD_ADDR(par, regno);
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TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
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TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
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TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
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}
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return 0;
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@ -1317,7 +1330,7 @@ tgafb_init_fix(struct fb_info *info)
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info->fix.type_aux = 0;
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info->fix.visual = (tga_type == TGA_TYPE_8PLANE
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? FB_VISUAL_PSEUDOCOLOR
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: FB_VISUAL_TRUECOLOR);
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: FB_VISUAL_DIRECTCOLOR);
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info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
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info->fix.smem_start = (size_t) par->tga_fb_base;
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