powerpc: Use 64k pages without needing cache-inhibited large pages
Some POWER5+ machines can do 64k hardware pages for normal memory but not for cache-inhibited pages. This patch lets us use 64k hardware pages for most user processes on such machines (assuming the kernel has been configured with CONFIG_PPC_64K_PAGES=y). User processes start out using 64k pages and get switched to 4k pages if they use any non-cacheable mappings. With this, we use 64k pages for the vmalloc region and 4k pages for the imalloc region. If anything creates a non-cacheable mapping in the vmalloc region, the vmalloc region will get switched to 4k pages. I don't know of any driver other than the DRM that would do this, though, and these machines don't have AGP. When a region gets switched from 64k pages to 4k pages, we do not have to clear out all the 64k HPTEs from the hash table immediately. We use the _PAGE_COMBO bit in the Linux PTE to indicate whether the page was hashed in as a 64k page or a set of 4k pages. If hash_page is trying to insert a 4k page for a Linux PTE and it sees that it has already been inserted as a 64k page, it first invalidates the 64k HPTE before inserting the 4k HPTE. The hash invalidation routines also use the _PAGE_COMBO bit, to determine whether to look for a 64k HPTE or a set of 4k HPTEs to remove. With those two changes, we can tolerate a mix of 4k and 64k HPTEs in the hash table, and they will all get removed when the address space is torn down. Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
parent
31925323b1
commit
bf72aeba2f
@ -122,6 +122,8 @@ int main(void)
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DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));
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DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));
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DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
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DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, context.sllp));
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DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp));
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#ifdef CONFIG_HUGETLB_PAGE
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DEFINE(PACALOWHTLBAREAS, offsetof(struct paca_struct, context.low_htlb_areas));
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DEFINE(PACAHIGHHTLBAREAS, offsetof(struct paca_struct, context.high_htlb_areas));
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@ -948,7 +948,10 @@ static struct ibm_pa_feature {
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{CPU_FTR_CTRL, 0, 0, 3, 0},
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{CPU_FTR_NOEXECUTE, 0, 0, 6, 0},
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{CPU_FTR_NODSISRALIGN, 0, 1, 1, 1},
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#if 0
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/* put this back once we know how to test if firmware does 64k IO */
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{CPU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0},
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#endif
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};
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static void __init check_cpu_pa_features(unsigned long node)
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@ -369,6 +369,7 @@ _GLOBAL(__hash_page_4K)
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rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
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or r30,r30,r31
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ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED | _PAGE_HASHPTE
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oris r30,r30,_PAGE_COMBO@h
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/* Write the linux PTE atomically (setting busy) */
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stdcx. r30,0,r6
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bne- 1b
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@ -428,6 +429,14 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
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andi. r0,r31,_PAGE_HASHPTE
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li r26,0 /* Default hidx */
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beq htab_insert_pte
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/*
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* Check if the pte was already inserted into the hash table
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* as a 64k HW page, and invalidate the 64k HPTE if so.
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*/
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andis. r0,r31,_PAGE_COMBO@h
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beq htab_inval_old_hpte
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ld r6,STK_PARM(r6)(r1)
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ori r26,r6,0x8000 /* Load the hidx mask */
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ld r26,0(r26)
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@ -498,6 +507,19 @@ _GLOBAL(htab_call_hpte_remove)
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/* Try all again */
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b htab_insert_pte
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/*
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* Call out to C code to invalidate an 64k HW HPTE that is
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* useless now that the segment has been switched to 4k pages.
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*/
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htab_inval_old_hpte:
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mr r3,r29 /* virtual addr */
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mr r4,r31 /* PTE.pte */
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li r5,0 /* PTE.hidx */
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li r6,MMU_PAGE_64K /* psize */
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ld r7,STK_PARM(r8)(r1) /* local */
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bl .flush_hash_page
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b htab_insert_pte
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htab_bail_ok:
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li r3,0
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b htab_bail
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@ -638,6 +660,12 @@ _GLOBAL(__hash_page_64K)
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* is changing this PTE anyway and might hash it.
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*/
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bne- ht64_bail_ok
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BEGIN_FTR_SECTION
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/* Check if PTE has the cache-inhibit bit set */
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andi. r0,r31,_PAGE_NO_CACHE
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/* If so, bail out and refault as a 4k page */
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bne- ht64_bail_ok
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END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
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/* Prepare new PTE value (turn access RW into DIRTY, then
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* add BUSY,HASHPTE and ACCESSED)
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*/
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@ -92,10 +92,15 @@ unsigned long htab_size_bytes;
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unsigned long htab_hash_mask;
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int mmu_linear_psize = MMU_PAGE_4K;
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int mmu_virtual_psize = MMU_PAGE_4K;
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int mmu_vmalloc_psize = MMU_PAGE_4K;
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int mmu_io_psize = MMU_PAGE_4K;
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#ifdef CONFIG_HUGETLB_PAGE
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int mmu_huge_psize = MMU_PAGE_16M;
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unsigned int HPAGE_SHIFT;
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#endif
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#ifdef CONFIG_PPC_64K_PAGES
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int mmu_ci_restrictions;
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#endif
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/* There are definitions of page sizes arrays to be used when none
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* is provided by the firmware.
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@ -308,20 +313,31 @@ static void __init htab_init_page_sizes(void)
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else if (mmu_psize_defs[MMU_PAGE_1M].shift)
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mmu_linear_psize = MMU_PAGE_1M;
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#ifdef CONFIG_PPC_64K_PAGES
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/*
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* Pick a size for the ordinary pages. Default is 4K, we support
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* 64K if cache inhibited large pages are supported by the
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* processor
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* 64K for user mappings and vmalloc if supported by the processor.
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* We only use 64k for ioremap if the processor
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* (and firmware) support cache-inhibited large pages.
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* If not, we use 4k and set mmu_ci_restrictions so that
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* hash_page knows to switch processes that use cache-inhibited
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* mappings to 4k pages.
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*/
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#ifdef CONFIG_PPC_64K_PAGES
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if (mmu_psize_defs[MMU_PAGE_64K].shift &&
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cpu_has_feature(CPU_FTR_CI_LARGE_PAGE))
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if (mmu_psize_defs[MMU_PAGE_64K].shift) {
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mmu_virtual_psize = MMU_PAGE_64K;
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mmu_vmalloc_psize = MMU_PAGE_64K;
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if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE))
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mmu_io_psize = MMU_PAGE_64K;
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else
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mmu_ci_restrictions = 1;
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}
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#endif
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printk(KERN_DEBUG "Page orders: linear mapping = %d, others = %d\n",
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printk(KERN_DEBUG "Page orders: linear mapping = %d, "
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"virtual = %d, io = %d\n",
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mmu_psize_defs[mmu_linear_psize].shift,
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mmu_psize_defs[mmu_virtual_psize].shift);
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mmu_psize_defs[mmu_virtual_psize].shift,
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mmu_psize_defs[mmu_io_psize].shift);
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#ifdef CONFIG_HUGETLB_PAGE
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/* Init large page size. Currently, we pick 16M or 1M depending
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@ -556,6 +572,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
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pte_t *ptep;
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cpumask_t tmp;
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int rc, user_region = 0, local = 0;
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int psize;
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DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
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ea, access, trap);
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@ -575,10 +592,15 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
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return 1;
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}
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vsid = get_vsid(mm->context.id, ea);
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psize = mm->context.user_psize;
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break;
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case VMALLOC_REGION_ID:
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mm = &init_mm;
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vsid = get_kernel_vsid(ea);
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if (ea < VMALLOC_END)
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psize = mmu_vmalloc_psize;
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else
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psize = mmu_io_psize;
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break;
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default:
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/* Not a valid range
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@ -629,7 +651,40 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
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#ifndef CONFIG_PPC_64K_PAGES
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rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
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#else
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if (mmu_virtual_psize == MMU_PAGE_64K)
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if (mmu_ci_restrictions) {
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/* If this PTE is non-cacheable, switch to 4k */
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if (psize == MMU_PAGE_64K &&
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(pte_val(*ptep) & _PAGE_NO_CACHE)) {
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if (user_region) {
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psize = MMU_PAGE_4K;
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mm->context.user_psize = MMU_PAGE_4K;
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mm->context.sllp = SLB_VSID_USER |
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mmu_psize_defs[MMU_PAGE_4K].sllp;
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} else if (ea < VMALLOC_END) {
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/*
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* some driver did a non-cacheable mapping
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* in vmalloc space, so switch vmalloc
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* to 4k pages
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*/
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printk(KERN_ALERT "Reducing vmalloc segment "
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"to 4kB pages because of "
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"non-cacheable mapping\n");
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psize = mmu_vmalloc_psize = MMU_PAGE_4K;
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}
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}
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if (user_region) {
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if (psize != get_paca()->context.user_psize) {
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get_paca()->context = mm->context;
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slb_flush_and_rebolt();
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}
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} else if (get_paca()->vmalloc_sllp !=
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mmu_psize_defs[mmu_vmalloc_psize].sllp) {
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get_paca()->vmalloc_sllp =
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mmu_psize_defs[mmu_vmalloc_psize].sllp;
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slb_flush_and_rebolt();
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}
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}
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if (psize == MMU_PAGE_64K)
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rc = __hash_page_64K(ea, access, vsid, ptep, trap, local);
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else
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rc = __hash_page_4K(ea, access, vsid, ptep, trap, local);
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@ -681,7 +736,18 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
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#ifndef CONFIG_PPC_64K_PAGES
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__hash_page_4K(ea, access, vsid, ptep, trap, local);
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#else
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if (mmu_virtual_psize == MMU_PAGE_64K)
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if (mmu_ci_restrictions) {
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/* If this PTE is non-cacheable, switch to 4k */
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if (mm->context.user_psize == MMU_PAGE_64K &&
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(pte_val(*ptep) & _PAGE_NO_CACHE)) {
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mm->context.user_psize = MMU_PAGE_4K;
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mm->context.sllp = SLB_VSID_USER |
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mmu_psize_defs[MMU_PAGE_4K].sllp;
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get_paca()->context = mm->context;
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slb_flush_and_rebolt();
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}
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}
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if (mm->context.user_psize == MMU_PAGE_64K)
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__hash_page_64K(ea, access, vsid, ptep, trap, local);
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else
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__hash_page_4K(ea, access, vsid, ptep, trap, local);
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@ -49,6 +49,9 @@ int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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}
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mm->context.id = index;
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mm->context.user_psize = mmu_virtual_psize;
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mm->context.sllp = SLB_VSID_USER |
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mmu_psize_defs[mmu_virtual_psize].sllp;
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return 0;
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}
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@ -60,19 +60,19 @@ static inline void create_slbe(unsigned long ea, unsigned long flags,
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: "memory" );
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}
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static void slb_flush_and_rebolt(void)
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void slb_flush_and_rebolt(void)
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{
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/* If you change this make sure you change SLB_NUM_BOLTED
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* appropriately too. */
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unsigned long linear_llp, virtual_llp, lflags, vflags;
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unsigned long linear_llp, vmalloc_llp, lflags, vflags;
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unsigned long ksp_esid_data;
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WARN_ON(!irqs_disabled());
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linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
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virtual_llp = mmu_psize_defs[mmu_virtual_psize].sllp;
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vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
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lflags = SLB_VSID_KERNEL | linear_llp;
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vflags = SLB_VSID_KERNEL | virtual_llp;
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vflags = SLB_VSID_KERNEL | vmalloc_llp;
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ksp_esid_data = mk_esid_data(get_paca()->kstack, 2);
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if ((ksp_esid_data & ESID_MASK) == PAGE_OFFSET)
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@ -164,11 +164,10 @@ static inline void patch_slb_encoding(unsigned int *insn_addr,
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void slb_initialize(void)
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{
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unsigned long linear_llp, virtual_llp;
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unsigned long linear_llp, vmalloc_llp, io_llp;
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static int slb_encoding_inited;
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extern unsigned int *slb_miss_kernel_load_linear;
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extern unsigned int *slb_miss_kernel_load_virtual;
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extern unsigned int *slb_miss_user_load_normal;
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extern unsigned int *slb_miss_kernel_load_io;
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#ifdef CONFIG_HUGETLB_PAGE
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extern unsigned int *slb_miss_user_load_huge;
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unsigned long huge_llp;
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@ -178,18 +177,19 @@ void slb_initialize(void)
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/* Prepare our SLB miss handler based on our page size */
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linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
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virtual_llp = mmu_psize_defs[mmu_virtual_psize].sllp;
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io_llp = mmu_psize_defs[mmu_io_psize].sllp;
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vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
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get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
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if (!slb_encoding_inited) {
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slb_encoding_inited = 1;
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patch_slb_encoding(slb_miss_kernel_load_linear,
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SLB_VSID_KERNEL | linear_llp);
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patch_slb_encoding(slb_miss_kernel_load_virtual,
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SLB_VSID_KERNEL | virtual_llp);
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patch_slb_encoding(slb_miss_user_load_normal,
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SLB_VSID_USER | virtual_llp);
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patch_slb_encoding(slb_miss_kernel_load_io,
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SLB_VSID_KERNEL | io_llp);
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DBG("SLB: linear LLP = %04x\n", linear_llp);
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DBG("SLB: virtual LLP = %04x\n", virtual_llp);
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DBG("SLB: io LLP = %04x\n", io_llp);
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#ifdef CONFIG_HUGETLB_PAGE
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patch_slb_encoding(slb_miss_user_load_huge,
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SLB_VSID_USER | huge_llp);
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@ -204,7 +204,7 @@ void slb_initialize(void)
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unsigned long lflags, vflags;
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lflags = SLB_VSID_KERNEL | linear_llp;
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vflags = SLB_VSID_KERNEL | virtual_llp;
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vflags = SLB_VSID_KERNEL | vmalloc_llp;
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/* Invalidate the entire SLB (even slot 0) & all the ERATS */
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asm volatile("isync":::"memory");
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@ -212,7 +212,6 @@ void slb_initialize(void)
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asm volatile("isync; slbia; isync":::"memory");
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create_slbe(PAGE_OFFSET, lflags, 0);
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/* VMALLOC space has 4K pages always for now */
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create_slbe(VMALLOC_START, vflags, 1);
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/* We don't bolt the stack for the time being - we're in boot,
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@ -59,10 +59,19 @@ _GLOBAL(slb_miss_kernel_load_linear)
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li r11,0
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b slb_finish_load
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1: /* vmalloc/ioremap mapping encoding bits, the "li" instruction below
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1: /* vmalloc/ioremap mapping encoding bits, the "li" instructions below
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* will be patched by the kernel at boot
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*/
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_GLOBAL(slb_miss_kernel_load_virtual)
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BEGIN_FTR_SECTION
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/* check whether this is in vmalloc or ioremap space */
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clrldi r11,r10,48
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cmpldi r11,(VMALLOC_SIZE >> 28) - 1
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bgt 5f
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lhz r11,PACAVMALLOCSLLP(r13)
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b slb_finish_load
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5:
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END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
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_GLOBAL(slb_miss_kernel_load_io)
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li r11,0
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b slb_finish_load
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@ -96,9 +105,7 @@ _GLOBAL(slb_miss_user_load_huge)
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1:
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#endif /* CONFIG_HUGETLB_PAGE */
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_GLOBAL(slb_miss_user_load_normal)
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li r11,0
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lhz r11,PACACONTEXTSLLP(r13)
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2:
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ld r9,PACACONTEXTID(r13)
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rldimi r10,r9,USER_ESID_BITS,0
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@ -131,7 +131,7 @@ void hpte_update(struct mm_struct *mm, unsigned long addr,
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{
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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unsigned long vsid;
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unsigned int psize = mmu_virtual_psize;
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unsigned int psize;
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int i;
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i = batch->index;
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@ -148,7 +148,8 @@ void hpte_update(struct mm_struct *mm, unsigned long addr,
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#else
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BUG();
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#endif
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}
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} else
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psize = pte_pagesize_index(pte);
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/*
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* This can happen when we are in the middle of a TLB batch and
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@ -165,6 +165,16 @@ struct mmu_psize_def
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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extern int mmu_linear_psize;
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extern int mmu_virtual_psize;
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extern int mmu_vmalloc_psize;
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extern int mmu_io_psize;
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/*
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* If the processor supports 64k normal pages but not 64k cache
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* inhibited pages, we have to be prepared to switch processes
|
||||
* to use 4k pages when they create cache-inhibited mappings.
|
||||
* If this is the case, mmu_ci_restrictions will be set to 1.
|
||||
*/
|
||||
extern int mmu_ci_restrictions;
|
||||
|
||||
#ifdef CONFIG_HUGETLB_PAGE
|
||||
/*
|
||||
@ -256,6 +266,7 @@ extern long iSeries_hpte_insert(unsigned long hpte_group,
|
||||
|
||||
extern void stabs_alloc(void);
|
||||
extern void slb_initialize(void);
|
||||
extern void slb_flush_and_rebolt(void);
|
||||
extern void stab_initialize(unsigned long stab);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
@ -359,6 +370,8 @@ typedef unsigned long mm_context_id_t;
|
||||
|
||||
typedef struct {
|
||||
mm_context_id_t id;
|
||||
u16 user_psize; /* page size index */
|
||||
u16 sllp; /* SLB entry page size encoding */
|
||||
#ifdef CONFIG_HUGETLB_PAGE
|
||||
u16 low_htlb_areas, high_htlb_areas;
|
||||
#endif
|
||||
|
@ -81,6 +81,7 @@ struct paca_struct {
|
||||
* on the linear mapping */
|
||||
|
||||
mm_context_t context;
|
||||
u16 vmalloc_sllp;
|
||||
u16 slb_cache[SLB_CACHE_ENTRIES];
|
||||
u16 slb_cache_ptr;
|
||||
|
||||
|
@ -78,6 +78,8 @@
|
||||
|
||||
#define pte_iterate_hashed_end() } while(0)
|
||||
|
||||
#define pte_pagesize_index(pte) MMU_PAGE_4K
|
||||
|
||||
/*
|
||||
* 4-level page tables related bits
|
||||
*/
|
||||
|
@ -90,6 +90,8 @@
|
||||
|
||||
#define pte_iterate_hashed_end() } while(0); } } while(0)
|
||||
|
||||
#define pte_pagesize_index(pte) \
|
||||
(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __KERNEL__ */
|
||||
|
@ -47,8 +47,8 @@ struct mm_struct;
|
||||
/*
|
||||
* Define the address range of the vmalloc VM area.
|
||||
*/
|
||||
#define VMALLOC_START (0xD000000000000000ul)
|
||||
#define VMALLOC_SIZE (0x80000000000UL)
|
||||
#define VMALLOC_START ASM_CONST(0xD000000000000000)
|
||||
#define VMALLOC_SIZE ASM_CONST(0x80000000000)
|
||||
#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
|
||||
|
||||
/*
|
||||
@ -413,12 +413,6 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
|
||||
flush_tlb_pending();
|
||||
}
|
||||
pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
|
||||
|
||||
#ifdef CONFIG_PPC_64K_PAGES
|
||||
if (mmu_virtual_psize != MMU_PAGE_64K)
|
||||
pte = __pte(pte_val(pte) | _PAGE_COMBO);
|
||||
#endif /* CONFIG_PPC_64K_PAGES */
|
||||
|
||||
*ptep = pte;
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user