mvpp2: XDP TX support
Add the transmit part of XDP support, which includes: - support for XDP_TX in mvpp2_xdp() - .ndo_xdp_xmit hook for AF_XDP and XDP_REDIRECT with mvpp2 as destination mvpp2_xdp_submit_frame() is a generic function which is called by mvpp2_xdp_xmit_back() when doing XDP_TX, and by mvpp2_xdp_xmit when doing AF_XDP or XDP_REDIRECT target. The buffer allocation has been reworked to be able to map the buffers as DMA_FROM_DEVICE or DMA_BIDIRECTIONAL depending if native XDP is in use or not. Co-developed-by: Sven Auhagen <sven.auhagen@voleatech.de> Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de> Signed-off-by: Matteo Croce <mcroce@microsoft.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matteo Croce
David S. Miller
parent
07dd0a7aae
commit
c2d6fe6163
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@ -1082,9 +1082,20 @@ struct mvpp2_rx_desc {
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};
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};
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enum mvpp2_tx_buf_type {
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MVPP2_TYPE_SKB,
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MVPP2_TYPE_XDP_TX,
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MVPP2_TYPE_XDP_NDO,
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};
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struct mvpp2_txq_pcpu_buf {
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enum mvpp2_tx_buf_type type;
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/* Transmitted SKB */
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struct sk_buff *skb;
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union {
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struct xdp_frame *xdpf;
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struct sk_buff *skb;
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};
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/* Physical address of transmitted buffer */
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dma_addr_t dma;
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@ -97,7 +97,8 @@ static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
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}
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static struct page_pool *
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mvpp2_create_page_pool(struct device *dev, int num, int len)
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mvpp2_create_page_pool(struct device *dev, int num, int len,
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enum dma_data_direction dma_dir)
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{
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struct page_pool_params pp_params = {
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/* internal DMA mapping in page_pool */
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@ -105,7 +106,7 @@ mvpp2_create_page_pool(struct device *dev, int num, int len)
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.pool_size = num,
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.nid = NUMA_NO_NODE,
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.dev = dev,
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.dma_dir = DMA_FROM_DEVICE,
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.dma_dir = dma_dir,
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.offset = MVPP2_SKB_HEADROOM,
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.max_len = len,
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};
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@ -299,12 +300,17 @@ static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
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static void mvpp2_txq_inc_put(struct mvpp2_port *port,
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struct mvpp2_txq_pcpu *txq_pcpu,
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struct sk_buff *skb,
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struct mvpp2_tx_desc *tx_desc)
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void *data,
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struct mvpp2_tx_desc *tx_desc,
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enum mvpp2_tx_buf_type buf_type)
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{
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struct mvpp2_txq_pcpu_buf *tx_buf =
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txq_pcpu->buffs + txq_pcpu->txq_put_index;
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tx_buf->skb = skb;
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tx_buf->type = buf_type;
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if (buf_type == MVPP2_TYPE_SKB)
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tx_buf->skb = data;
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else
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tx_buf->xdpf = data;
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tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
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tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
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mvpp2_txdesc_offset_get(port, tx_desc);
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@ -527,9 +533,6 @@ static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
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int buf_num;
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u32 val;
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if (priv->percpu_pools)
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page_pool_destroy(priv->page_pool[bm_pool->id]);
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buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
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mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num);
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@ -545,6 +548,9 @@ static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
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val |= MVPP2_BM_STOP_MASK;
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mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
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if (priv->percpu_pools)
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page_pool_destroy(priv->page_pool[bm_pool->id]);
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dma_free_coherent(dev, bm_pool->size_bytes,
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bm_pool->virt_addr,
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bm_pool->dma_addr);
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@ -580,9 +586,19 @@ static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
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static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
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{
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enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
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int i, err, poolnum = MVPP2_BM_POOLS_NUM;
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struct mvpp2_port *port;
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if (priv->percpu_pools) {
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for (i = 0; i < priv->port_count; i++) {
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port = priv->port_list[i];
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if (port->xdp_prog) {
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dma_dir = DMA_BIDIRECTIONAL;
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break;
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}
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}
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poolnum = mvpp2_get_nrxqs(priv) * 2;
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for (i = 0; i < poolnum; i++) {
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/* the pool in use */
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@ -591,7 +607,8 @@ static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
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priv->page_pool[i] =
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mvpp2_create_page_pool(dev,
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mvpp2_pools[pn].buf_num,
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mvpp2_pools[pn].pkt_size);
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mvpp2_pools[pn].pkt_size,
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dma_dir);
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if (IS_ERR(priv->page_pool[i]))
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return PTR_ERR(priv->page_pool[i]);
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}
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@ -2318,11 +2335,15 @@ static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
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struct mvpp2_txq_pcpu_buf *tx_buf =
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txq_pcpu->buffs + txq_pcpu->txq_get_index;
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if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma))
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if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) &&
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tx_buf->type != MVPP2_TYPE_XDP_TX)
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dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
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tx_buf->size, DMA_TO_DEVICE);
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if (tx_buf->skb)
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if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb)
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dev_kfree_skb_any(tx_buf->skb);
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else if (tx_buf->type == MVPP2_TYPE_XDP_TX ||
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tx_buf->type == MVPP2_TYPE_XDP_NDO)
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xdp_return_frame(tx_buf->xdpf);
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mvpp2_txq_inc_get(txq_pcpu);
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}
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@ -2810,7 +2831,7 @@ static int mvpp2_setup_rxqs(struct mvpp2_port *port)
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static int mvpp2_setup_txqs(struct mvpp2_port *port)
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{
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struct mvpp2_tx_queue *txq;
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int queue, err, cpu;
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int queue, err;
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for (queue = 0; queue < port->ntxqs; queue++) {
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txq = port->txqs[queue];
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@ -2819,8 +2840,8 @@ static int mvpp2_setup_txqs(struct mvpp2_port *port)
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goto err_cleanup;
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/* Assign this queue to a CPU */
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cpu = queue % num_present_cpus();
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netif_set_xps_queue(port->dev, cpumask_of(cpu), queue);
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if (queue < num_possible_cpus())
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netif_set_xps_queue(port->dev, cpumask_of(queue), queue);
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}
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if (port->has_tx_irqs) {
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@ -3039,6 +3060,164 @@ static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
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return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
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}
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static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte)
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{
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unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
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struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
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struct mvpp2_tx_queue *aggr_txq;
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struct mvpp2_txq_pcpu *txq_pcpu;
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struct mvpp2_tx_queue *txq;
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struct netdev_queue *nq;
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txq = port->txqs[txq_id];
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txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
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nq = netdev_get_tx_queue(port->dev, txq_id);
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aggr_txq = &port->priv->aggr_txqs[thread];
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txq_pcpu->reserved_num -= nxmit;
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txq_pcpu->count += nxmit;
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aggr_txq->count += nxmit;
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/* Enable transmit */
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wmb();
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mvpp2_aggr_txq_pend_desc_add(port, nxmit);
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if (txq_pcpu->count >= txq_pcpu->stop_threshold)
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netif_tx_stop_queue(nq);
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u64_stats_update_begin(&stats->syncp);
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stats->tx_bytes += nxmit_byte;
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stats->tx_packets += nxmit;
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u64_stats_update_end(&stats->syncp);
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/* Finalize TX processing */
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if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
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mvpp2_txq_done(port, txq, txq_pcpu);
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}
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static int
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mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id,
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struct xdp_frame *xdpf, bool dma_map)
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{
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unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
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u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE |
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MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
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enum mvpp2_tx_buf_type buf_type;
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struct mvpp2_txq_pcpu *txq_pcpu;
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struct mvpp2_tx_queue *aggr_txq;
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struct mvpp2_tx_desc *tx_desc;
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struct mvpp2_tx_queue *txq;
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int ret = MVPP2_XDP_TX;
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dma_addr_t dma_addr;
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txq = port->txqs[txq_id];
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txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
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aggr_txq = &port->priv->aggr_txqs[thread];
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/* Check number of available descriptors */
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if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) ||
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mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) {
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ret = MVPP2_XDP_DROPPED;
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goto out;
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}
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/* Get a descriptor for the first part of the packet */
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tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
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mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
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mvpp2_txdesc_size_set(port, tx_desc, xdpf->len);
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if (dma_map) {
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/* XDP_REDIRECT or AF_XDP */
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dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data,
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xdpf->len, DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
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mvpp2_txq_desc_put(txq);
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ret = MVPP2_XDP_DROPPED;
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goto out;
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}
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buf_type = MVPP2_TYPE_XDP_NDO;
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} else {
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/* XDP_TX */
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struct page *page = virt_to_page(xdpf->data);
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dma_addr = page_pool_get_dma_addr(page) +
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sizeof(*xdpf) + xdpf->headroom;
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dma_sync_single_for_device(port->dev->dev.parent, dma_addr,
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xdpf->len, DMA_BIDIRECTIONAL);
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buf_type = MVPP2_TYPE_XDP_TX;
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}
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mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr);
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mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
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mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type);
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out:
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return ret;
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}
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static int
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mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp)
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{
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struct xdp_frame *xdpf;
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u16 txq_id;
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int ret;
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xdpf = xdp_convert_buff_to_frame(xdp);
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if (unlikely(!xdpf))
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return MVPP2_XDP_DROPPED;
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/* The first of the TX queues are used for XPS,
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* the second half for XDP_TX
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*/
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txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
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ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false);
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if (ret == MVPP2_XDP_TX)
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mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len);
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return ret;
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}
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static int
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mvpp2_xdp_xmit(struct net_device *dev, int num_frame,
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struct xdp_frame **frames, u32 flags)
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{
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struct mvpp2_port *port = netdev_priv(dev);
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int i, nxmit_byte = 0, nxmit = num_frame;
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u16 txq_id;
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u32 ret;
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if (unlikely(test_bit(0, &port->state)))
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return -ENETDOWN;
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if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
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return -EINVAL;
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/* The first of the TX queues are used for XPS,
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* the second half for XDP_TX
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*/
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txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
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for (i = 0; i < num_frame; i++) {
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ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true);
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if (ret == MVPP2_XDP_TX) {
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nxmit_byte += frames[i]->len;
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} else {
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xdp_return_frame_rx_napi(frames[i]);
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nxmit--;
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}
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}
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if (nxmit > 0)
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mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte);
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return nxmit;
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}
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static int
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mvpp2_run_xdp(struct mvpp2_port *port, struct mvpp2_rx_queue *rxq,
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struct bpf_prog *prog, struct xdp_buff *xdp,
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@ -3069,6 +3248,13 @@ mvpp2_run_xdp(struct mvpp2_port *port, struct mvpp2_rx_queue *rxq,
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ret = MVPP2_XDP_REDIR;
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}
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break;
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case XDP_TX:
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ret = mvpp2_xdp_xmit_back(port, xdp);
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if (ret != MVPP2_XDP_TX) {
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page = virt_to_head_page(xdp->data);
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page_pool_put_page(pp, page, sync, true);
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}
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break;
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default:
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bpf_warn_invalid_xdp_action(act);
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fallthrough;
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@ -3090,6 +3276,7 @@ static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
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int rx_todo, struct mvpp2_rx_queue *rxq)
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{
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struct net_device *dev = port->dev;
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enum dma_data_direction dma_dir;
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struct bpf_prog *xdp_prog;
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struct xdp_buff xdp;
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int rx_received;
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@ -3139,13 +3326,19 @@ static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
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if (rx_status & MVPP2_RXD_ERR_SUMMARY)
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goto err_drop_frame;
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if (port->priv->percpu_pools) {
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pp = port->priv->page_pool[pool];
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dma_dir = page_pool_get_dma_dir(pp);
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} else {
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dma_dir = DMA_FROM_DEVICE;
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}
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dma_sync_single_for_cpu(dev->dev.parent, dma_addr,
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rx_bytes + MVPP2_MH_SIZE,
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DMA_FROM_DEVICE);
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prefetch(data);
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dma_dir);
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if (port->priv->percpu_pools)
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pp = port->priv->page_pool[pool];
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/* Prefetch header */
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prefetch(data);
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if (bm_pool->frag_size > PAGE_SIZE)
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frag_size = 0;
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@ -3218,6 +3411,9 @@ static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
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rcu_read_unlock();
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if (xdp_ret & MVPP2_XDP_REDIR)
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xdp_do_flush_map();
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if (rcvd_pkts) {
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struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
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@ -3284,11 +3480,11 @@ static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
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/* Last descriptor */
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mvpp2_txdesc_cmd_set(port, tx_desc,
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MVPP2_TXD_L_DESC);
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mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
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mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
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} else {
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/* Descriptor in the middle: Not First, Not Last */
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mvpp2_txdesc_cmd_set(port, tx_desc, 0);
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mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
|
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mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -3326,7 +3522,7 @@ static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
|
|||
mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
|
||||
MVPP2_TXD_F_DESC |
|
||||
MVPP2_TXD_PADDING_DISABLE);
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
|
||||
}
|
||||
|
||||
static inline int mvpp2_tso_put_data(struct sk_buff *skb,
|
||||
|
|
@ -3355,14 +3551,14 @@ static inline int mvpp2_tso_put_data(struct sk_buff *skb,
|
|||
if (!left) {
|
||||
mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
|
||||
if (last) {
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
mvpp2_txdesc_cmd_set(port, tx_desc, 0);
|
||||
}
|
||||
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -3475,12 +3671,12 @@ static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
|
|||
/* First and Last descriptor */
|
||||
tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
|
||||
mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
|
||||
} else {
|
||||
/* First but not Last */
|
||||
tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
|
||||
mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
|
||||
mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
|
||||
|
||||
/* Continue with other skb fragments */
|
||||
if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
|
||||
|
|
@ -4159,6 +4355,33 @@ static int mvpp2_change_mtu(struct net_device *dev, int mtu)
|
|||
return err;
|
||||
}
|
||||
|
||||
static int mvpp2_check_pagepool_dma(struct mvpp2_port *port)
|
||||
{
|
||||
enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
|
||||
struct mvpp2 *priv = port->priv;
|
||||
int err = -1, i;
|
||||
|
||||
if (!priv->percpu_pools)
|
||||
return err;
|
||||
|
||||
if (!priv->page_pool)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < priv->port_count; i++) {
|
||||
port = priv->port_list[i];
|
||||
if (port->xdp_prog) {
|
||||
dma_dir = DMA_BIDIRECTIONAL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* All pools are equal in terms of DMA direction */
|
||||
if (priv->page_pool[0]->p.dma_dir != dma_dir)
|
||||
err = mvpp2_bm_switch_buffers(priv, true);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void
|
||||
mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
|
||||
{
|
||||
|
|
@ -4268,13 +4491,15 @@ static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf)
|
|||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
/* device is up and bpf is added/removed, must setup the RX queues */
|
||||
if (running && reset) {
|
||||
mvpp2_stop_dev(port);
|
||||
mvpp2_cleanup_rxqs(port);
|
||||
mvpp2_cleanup_txqs(port);
|
||||
if (port->ntxqs < num_possible_cpus() * 2) {
|
||||
NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU");
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
/* device is up and bpf is added/removed, must setup the RX queues */
|
||||
if (running && reset)
|
||||
mvpp2_stop(port->dev);
|
||||
|
||||
old_prog = xchg(&port->xdp_prog, prog);
|
||||
if (old_prog)
|
||||
bpf_prog_put(old_prog);
|
||||
|
|
@ -4284,21 +4509,11 @@ static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf)
|
|||
return 0;
|
||||
|
||||
/* device was up, restore the link */
|
||||
if (running) {
|
||||
int ret = mvpp2_setup_rxqs(port);
|
||||
if (running)
|
||||
mvpp2_open(port->dev);
|
||||
|
||||
if (ret) {
|
||||
netdev_err(port->dev, "mvpp2_setup_rxqs failed\n");
|
||||
return ret;
|
||||
}
|
||||
ret = mvpp2_setup_txqs(port);
|
||||
if (ret) {
|
||||
netdev_err(port->dev, "mvpp2_setup_txqs failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
mvpp2_start_dev(port);
|
||||
}
|
||||
/* Check Page Pool DMA Direction */
|
||||
mvpp2_check_pagepool_dma(port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -4669,6 +4884,7 @@ static const struct net_device_ops mvpp2_netdev_ops = {
|
|||
.ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
|
||||
.ndo_set_features = mvpp2_set_features,
|
||||
.ndo_bpf = mvpp2_xdp,
|
||||
.ndo_xdp_xmit = mvpp2_xdp_xmit,
|
||||
};
|
||||
|
||||
static const struct ethtool_ops mvpp2_eth_tool_ops = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user